| Message ID | 20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-0-87d669674c00@baylibre.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | iio: add support for the ad3552r AXI DAC IP | expand |
On 9/5/24 10:17 AM, Angelo Dureghello wrote: > The serie comes from the previously discussed RFC, that i > converted to a normal patch from this v2. > > Purpose is to add ad3552r AXI DAC (fpga-based) support. > > The fpga DAC IP has been created to reach the maximum speed > (33MUPS) supported from the ad3552r. To obtain the maximum > transfer rate, the custom module has been implemented using > the QSPI lines in DDR mode, using a dma buffer. > > The design is actually using the DAC backend since the register > map is the same of the generic DAC IP, except for some customized > bitfields. For this reason, a new "compatible" has been added > in adi-axi-dac.c. > > Also, backend has been extended with all the needed functions > needed for this use case, keeping the names gneric. > > Note: the following patch is actually for linux-iio/testing > --- > Changes in v2: > - use unsigned int on bus_reg_read/write > - add a compatible in axi-dac backend for the ad3552r DAC IP > - minor code alignment fixes > - fix a return value not checked > - change devicetree structure setting ad3552r-axi as a backend > subnode > - add synchronous_mode_available in the ABI doc > > Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> > Co-developed-by: David Lechner <dlechner@baylibre.com> > Co-developed-by: Nuno Sá <nuno.sa@analog.com> > We didn't actually write any of the code, so I don't think Co-developed-by: is the right way to give us credit. But we can give our Reviewed-by: tags when this is ready to be merged.
On Thu, Sep 05, 2024 at 05:17:30PM +0200, Angelo Dureghello wrote: > The serie comes from the previously discussed RFC, that i > converted to a normal patch from this v2. > > Purpose is to add ad3552r AXI DAC (fpga-based) support. > > The fpga DAC IP has been created to reach the maximum speed > (33MUPS) supported from the ad3552r. To obtain the maximum > transfer rate, the custom module has been implemented using > the QSPI lines in DDR mode, using a dma buffer. > > The design is actually using the DAC backend since the register > map is the same of the generic DAC IP, except for some customized > bitfields. For this reason, a new "compatible" has been added > in adi-axi-dac.c. > > Also, backend has been extended with all the needed functions > needed for this use case, keeping the names gneric. > > Note: the following patch is actually for linux-iio/testing > --- > Changes in v2: > - use unsigned int on bus_reg_read/write > - add a compatible in axi-dac backend for the ad3552r DAC IP > - minor code alignment fixes > - fix a return value not checked > - change devicetree structure setting ad3552r-axi as a backend > subnode > - add synchronous_mode_available in the ABI doc Please give reviewers a chance to response to in-progress discussion on a version before sending a new one. I've left a couple of responses to v1 that I only had a chance to reply to today due to travel.
Hi Conor, On 06/09/24 11:07 AM, Conor Dooley wrote: > On Thu, Sep 05, 2024 at 05:17:30PM +0200, Angelo Dureghello wrote: >> The serie comes from the previously discussed RFC, that i >> converted to a normal patch from this v2. >> >> Purpose is to add ad3552r AXI DAC (fpga-based) support. >> >> The fpga DAC IP has been created to reach the maximum speed >> (33MUPS) supported from the ad3552r. To obtain the maximum >> transfer rate, the custom module has been implemented using >> the QSPI lines in DDR mode, using a dma buffer. >> >> The design is actually using the DAC backend since the register >> map is the same of the generic DAC IP, except for some customized >> bitfields. For this reason, a new "compatible" has been added >> in adi-axi-dac.c. >> >> Also, backend has been extended with all the needed functions >> needed for this use case, keeping the names gneric. >> >> Note: the following patch is actually for linux-iio/testing >> --- >> Changes in v2: >> - use unsigned int on bus_reg_read/write >> - add a compatible in axi-dac backend for the ad3552r DAC IP >> - minor code alignment fixes >> - fix a return value not checked >> - change devicetree structure setting ad3552r-axi as a backend >> subnode >> - add synchronous_mode_available in the ABI doc > Please give reviewers a chance to response to in-progress discussion on > a version before sending a new one. I've left a couple of responses to > v1 that I only had a chance to reply to today due to travel. sure, will wait some more days next time. Regards,
The serie comes from the previously discussed RFC, that i converted to a normal patch from this v2. Purpose is to add ad3552r AXI DAC (fpga-based) support. The fpga DAC IP has been created to reach the maximum speed (33MUPS) supported from the ad3552r. To obtain the maximum transfer rate, the custom module has been implemented using the QSPI lines in DDR mode, using a dma buffer. The design is actually using the DAC backend since the register map is the same of the generic DAC IP, except for some customized bitfields. For this reason, a new "compatible" has been added in adi-axi-dac.c. Also, backend has been extended with all the needed functions needed for this use case, keeping the names gneric. Note: the following patch is actually for linux-iio/testing --- Changes in v2: - use unsigned int on bus_reg_read/write - add a compatible in axi-dac backend for the ad3552r DAC IP - minor code alignment fixes - fix a return value not checked - change devicetree structure setting ad3552r-axi as a backend subnode - add synchronous_mode_available in the ABI doc Signed-off-by: Angelo Dureghello <adureghello@baylibre.com> Co-developed-by: David Lechner <dlechner@baylibre.com> Co-developed-by: Nuno Sá <nuno.sa@analog.com> --- Angelo Dureghello (9): dt-bindings: iio: dac: ad3552r: add io-backend property iio: backend: extend features iio: backend adi-axi-dac: extend features iio: backend adi-axi-dac: add registering of child fdt node dt-bindings: iio: dac: add ad3552r axi-dac compatible iio: dac: ad3552r: changes to use FIELD_PREP iio: dac: ad3552r: extract common code (no changes in behavior intended) iio: dac: ad3552r: add axi platform driver iio: ABI: add DAC sysfs synchronous_mode parameter Documentation/ABI/testing/sysfs-bus-iio-dac | 16 + .../devicetree/bindings/iio/dac/adi,ad3552r.yaml | 42 +- .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 1 + drivers/iio/dac/Kconfig | 11 + drivers/iio/dac/Makefile | 3 +- drivers/iio/dac/ad3552r-axi.c | 567 +++++++++++++++++++++ drivers/iio/dac/ad3552r-common.c | 163 ++++++ drivers/iio/dac/ad3552r.c | 394 +++----------- drivers/iio/dac/ad3552r.h | 199 ++++++++ drivers/iio/dac/adi-axi-dac.c | 282 +++++++++- drivers/iio/industrialio-backend.c | 157 ++++++ include/linux/iio/backend.h | 33 ++ 12 files changed, 1532 insertions(+), 336 deletions(-) --- base-commit: 8b6f7caca90addc22eb4ae958639048001096003 change-id: 20240905-wip-bl-ad3552r-axi-v0-iio-testing-1ef516b10ef0 Best regards,