diff mbox series

arm64: dts: imx8m*-venice-gw75xx: add Accelerometer device

Message ID 20240905183107.517244-1-tharvey@gateworks.com (mailing list archive)
State New
Headers show
Series arm64: dts: imx8m*-venice-gw75xx: add Accelerometer device | expand

Commit Message

Tim Harvey Sept. 5, 2024, 6:31 p.m. UTC 
The GW79xx has a LIS2DE12TR 3-axis accelerometer on the I2C bus with an
interrupt pin. Add it to the device-tree.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 .../boot/dts/freescale/imx8mm-venice-gw75xx.dtsi | 16 ++++++++++++++++
 .../boot/dts/freescale/imx8mp-venice-gw75xx.dtsi | 16 ++++++++++++++++
 2 files changed, 32 insertions(+)

Comments

Peng Fan Sept. 6, 2024, 8:14 a.m. UTC | #1 
> Subject: [PATCH] arm64: dts: imx8m*-venice-gw75xx: add
> Accelerometer device
> 
> The GW79xx has a LIS2DE12TR 3-axis accelerometer on the I2C bus
> with an interrupt pin. Add it to the device-tree.
> 
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---
>  .../boot/dts/freescale/imx8mm-venice-gw75xx.dtsi | 16
> ++++++++++++++++  .../boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
> | 16 ++++++++++++++++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
> index 5eb92005195c..417c19774b17 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
> @@ -116,6 +116,16 @@ &i2c2 {
>  	pinctrl-0 = <&pinctrl_i2c2>;
>  	status = "okay";
> 
> +	accelerometer@19 {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_accel>;
> +		compatible = "st,lis2de12";
> +		reg = <0x19>;

Nitpick:
compatible, reg should be top.
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html

> +		st,drdy-int-pin = <1>;
> +		interrupt-parent = <&gpio5>;
> +		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
>  	eeprom@52 {
>  		compatible = "atmel,24c32";
>  		reg = <0x52>;
> @@ -198,6 +208,12 @@ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4
> 		0x40000040 /* GPIOC */
>  		>;
>  	};
> 
> +	pinctrl_accel: accelgrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8
> 	0x159
> +		>;
> +	};
> +
>  	pinctrl_gpio_leds: gpioledgrp {
>  		fsl,pins = <
>  			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0
> 	0x6	/* LEDG */
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
> index 0d40cb0f05f6..797d1168f4f2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
> @@ -104,6 +104,16 @@ &i2c2 {
>  	pinctrl-0 = <&pinctrl_i2c2>;
>  	status = "okay";
> 
> +	accelerometer@19 {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_accel>;
> +		compatible = "st,lis2de12";
> +		reg = <0x19>;

Ditto.

> +		st,drdy-int-pin = <1>;

This should be at end.

Regards,
Peng.
> +		interrupt-parent = <&gpio5>;
> +		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
>  	eeprom@52 {
>  		compatible = "atmel,24c32";
>  		reg = <0x52>;
> @@ -204,6 +214,12 @@ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28
> 	0x40000106 /* PCI_WDIS# */
>  		>;
>  	};
> 
> +	pinctrl_accel: accelgrp {
> +		fsl,pins = <
> +
> 	MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08	0x159
> +		>;
> +	};
> +
>  	pinctrl_gpio_leds: gpioledgrp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22
> 	0x6	/* LEDG */
> --
> 2.25.1
>
Tim Harvey Sept. 9, 2024, 9:46 p.m. UTC | #2 
On Fri, Sep 6, 2024 at 1:14 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> > Subject: [PATCH] arm64: dts: imx8m*-venice-gw75xx: add
> > Accelerometer device
> >
> > The GW79xx has a LIS2DE12TR 3-axis accelerometer on the I2C bus
> > with an interrupt pin. Add it to the device-tree.
> >
> > Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> > ---
> >  .../boot/dts/freescale/imx8mm-venice-gw75xx.dtsi | 16
> > ++++++++++++++++  .../boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
> > | 16 ++++++++++++++++
> >  2 files changed, 32 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
> > index 5eb92005195c..417c19774b17 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
> > @@ -116,6 +116,16 @@ &i2c2 {
> >       pinctrl-0 = <&pinctrl_i2c2>;
> >       status = "okay";
> >
> > +     accelerometer@19 {
> > +             pinctrl-names = "default";
> > +             pinctrl-0 = <&pinctrl_accel>;
> > +             compatible = "st,lis2de12";
> > +             reg = <0x19>;
>
> Nitpick:
> compatible, reg should be top.
> https://docs.kernel.org/devicetree/bindings/dts-coding-style.html

Hi Peng,

Thanks, I will submit a v2

Tim
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
index 5eb92005195c..417c19774b17 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
@@ -116,6 +116,16 @@  &i2c2 {
 	pinctrl-0 = <&pinctrl_i2c2>;
 	status = "okay";
 
+	accelerometer@19 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_accel>;
+		compatible = "st,lis2de12";
+		reg = <0x19>;
+		st,drdy-int-pin = <1>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+	};
+
 	eeprom@52 {
 		compatible = "atmel,24c32";
 		reg = <0x52>;
@@ -198,6 +208,12 @@  MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000040 /* GPIOC */
 		>;
 	};
 
+	pinctrl_accel: accelgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8	0x159
+		>;
+	};
+
 	pinctrl_gpio_leds: gpioledgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x6	/* LEDG */
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
index 0d40cb0f05f6..797d1168f4f2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
@@ -104,6 +104,16 @@  &i2c2 {
 	pinctrl-0 = <&pinctrl_i2c2>;
 	status = "okay";
 
+	accelerometer@19 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_accel>;
+		compatible = "st,lis2de12";
+		reg = <0x19>;
+		st,drdy-int-pin = <1>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+	};
+
 	eeprom@52 {
 		compatible = "atmel,24c32";
 		reg = <0x52>;
@@ -204,6 +214,12 @@  MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCI_WDIS# */
 		>;
 	};
 
+	pinctrl_accel: accelgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08	0x159
+		>;
+	};
+
 	pinctrl_gpio_leds: gpioledgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x6	/* LEDG */