[v6,3/3] drm/rockchip: Add basic RK3588 HDMI output support

Message ID	20240906-b4-rk3588-bridge-upstream-v6-3-a3128fb103eb@collabora.com (mailing list archive)
State	New
Headers	show Return-Path: <linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org> sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 580B017E0E9C; Fri, 6 Sep 2024 03:18:02 +0200 (CEST) From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Date: Fri, 06 Sep 2024 04:17:42 +0300 Subject: [PATCH v6 3/3] drm/rockchip: Add basic RK3588 HDMI output support MIME-Version: 1.0 Message-Id: <20240906-b4-rk3588-bridge-upstream-v6-3-a3128fb103eb@collabora.com> References: <20240906-b4-rk3588-bridge-upstream-v6-0-a3128fb103eb@collabora.com> In-Reply-To: <20240906-b4-rk3588-bridge-upstream-v6-0-a3128fb103eb@collabora.com> To: Andrzej Hajda <andrzej.hajda@intel.com>, Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <rfoss@kernel.org>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Sandy Huang <hjc@rock-chips.com>, =?utf-8?q?Heiko_St=C3=BCbner?= <heiko@sntech.de>, Andy Yan <andy.yan@rock-chips.com>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Mark Yao <markyao0591@gmail.com>, Sascha Hauer <s.hauer@pengutronix.de> Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com, Alexandre ARNOUD <aarnoud@me.com>, Luis de Arquer <ldearquer@gmail.com>, Algea Cao <algea.cao@rock-chips.com> Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" <linux-rockchip-bounces@lists.infradead.org> Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org
Series	Add initial support for the Rockchip RK3588 HDMI TX Controller \| expand [v6,0/3] Add initial support for the Rockchip RK3588 HDMI TX Controller [v6,1/3] drm/bridge: synopsys: Add DW HDMI QP TX Controller support library [v6,2/3] dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX Controller [v6,3/3] drm/rockchip: Add basic RK3588 HDMI output support

Hi Cristian, kernel test robot noticed the following build warnings: [auto build test WARNING on 8400291e289ee6b2bf9779ff1c83a291501f017b] url: https://github.com/intel-lab-lkp/linux/commits/Cristian-Ciocaltea/drm-bridge-synopsys-Add-DW-HDMI-QP-TX-Controller-support-library/20240906-092027 base: 8400291e289ee6b2bf9779ff1c83a291501f017b patch link: https://lore.kernel.org/r/20240906-b4-rk3588-bridge-upstream-v6-3-a3128fb103eb%40collabora.com patch subject: [PATCH v6 3/3] drm/rockchip: Add basic RK3588 HDMI output support config: powerpc64-randconfig-r122-20240908 (https://download.01.org/0day-ci/archive/20240909/202409090615.l6BkuR5K-lkp@intel.com/config) compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18) reproduce: (https://download.01.org/0day-ci/archive/20240909/202409090615.l6BkuR5K-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202409090615.l6BkuR5K-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c:679:24: sparse: sparse: incorrect type in return expression (different address spaces) @@ expected struct dw_hdmi_qp * @@ got void [noderef] __iomem *[assigned] regs @@ drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c:679:24: sparse: expected struct dw_hdmi_qp * drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c:679:24: sparse: got void [noderef] __iomem *[assigned] regs vim +679 drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 653 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 654 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 655 struct drm_encoder *encoder, 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 656 const struct dw_hdmi_qp_plat_data *plat_data) 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 657 { 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 658 struct device *dev = &pdev->dev; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 659 struct dw_hdmi_qp *hdmi; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 660 void __iomem *regs; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 661 int ret; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 662 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 663 if (!plat_data->phy_ops || !plat_data->phy_ops->init || 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 664 !plat_data->phy_ops->disable || !plat_data->phy_ops->read_hpd) { 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 665 dev_err(dev, "Missing platform PHY ops\n"); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 666 return ERR_PTR(-ENODEV); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 667 } 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 668 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 669 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 670 if (!hdmi) 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 671 return ERR_PTR(-ENOMEM); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 672 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 673 INIT_DELAYED_WORK(&hdmi->scramb_work, dw_hdmi_qp_scramb_work); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 674 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 675 hdmi->dev = dev; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 676 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 677 regs = devm_platform_ioremap_resource(pdev, 0); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 678 if (IS_ERR(regs)) 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 @679 return regs; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 680 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 681 hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 682 if (IS_ERR(hdmi->regm)) { 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 683 dev_err(dev, "Failed to configure regmap\n"); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 684 return ERR_CAST(hdmi->regm); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 685 } 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 686 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 687 hdmi->phy.ops = plat_data->phy_ops; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 688 hdmi->phy.data = plat_data->phy_data; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 689 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 690 dw_hdmi_qp_init_hw(hdmi); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 691 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 692 ret = devm_request_threaded_irq(dev, plat_data->main_irq, 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 693 dw_hdmi_qp_main_hardirq, NULL, 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 694 IRQF_SHARED, dev_name(dev), hdmi); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 695 if (ret) 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 696 return ERR_PTR(ret); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 697 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 698 hdmi->bridge.driver_private = hdmi; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 699 hdmi->bridge.funcs = &dw_hdmi_qp_bridge_funcs; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 700 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 701 DRM_BRIDGE_OP_EDID | 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 702 DRM_BRIDGE_OP_HDMI | 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 703 DRM_BRIDGE_OP_HPD; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 704 hdmi->bridge.of_node = pdev->dev.of_node; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 705 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 706 hdmi->bridge.vendor = "Synopsys"; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 707 hdmi->bridge.product = "DW HDMI QP TX"; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 708 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 709 hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 710 if (IS_ERR(hdmi->bridge.ddc)) 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 711 hdmi->bridge.ddc = NULL; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 712 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 713 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 714 if (ret) 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 715 return ERR_PTR(ret); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 716 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 717 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 718 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 719 if (ret) 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 720 return ERR_PTR(ret); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 721 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 722 return hdmi; 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 723 } 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 724 EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind); 4ae2f13b217e6c Cristian Ciocaltea 2024-09-06 725

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 7df875e38517..4da7cef24f57 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -8,6 +8,7 @@ config DRM_ROCKCHIP select VIDEOMODE_HELPERS select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP select DRM_DW_HDMI if ROCKCHIP_DW_HDMI + select DRM_DW_HDMI_QP if ROCKCHIP_DW_HDMI_QP select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI select GENERIC_PHY if ROCKCHIP_DW_MIPI_DSI select GENERIC_PHY_MIPI_DPHY if ROCKCHIP_DW_MIPI_DSI @@ -63,6 +64,13 @@ config ROCKCHIP_DW_HDMI enable HDMI on RK3288 or RK3399 based SoC, you should select this option. +config ROCKCHIP_DW_HDMI_QP + bool "Rockchip specific extensions for Synopsys DW HDMI QP" + help + This selects support for Rockchip SoC specific extensions + for the Synopsys DesignWare HDMI QP driver. If you want to + enable HDMI on RK3588 based SoC, you should select this option. + config ROCKCHIP_DW_MIPI_DSI bool "Rockchip specific extensions for Synopsys DW MIPI DSI" select GENERIC_PHY_MIPI_DPHY diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index 3ff7b21c0414..3eab662a5a1d 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -11,6 +11,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o +rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI_QP) += dw_hdmi_qp-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c new file mode 100644 index 000000000000..a743ed3a2090 --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Collabora Ltd. + * + * Author: Algea Cao <algea.cao@rock-chips.com> + * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> + */ + +#include <linux/clk.h> +#include <linux/gpio/consumer.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/workqueue.h> + +#include <drm/bridge/dw_hdmi_qp.h> +#include <drm/drm_bridge_connector.h> +#include <drm/drm_of.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_simple_kms_helper.h> + +#include "rockchip_drm_drv.h" + +#define RK3588_GRF_SOC_CON2 0x0308 +#define RK3588_HDMI0_HPD_INT_MSK BIT(13) +#define RK3588_HDMI0_HPD_INT_CLR BIT(12) +#define RK3588_GRF_SOC_CON7 0x031c +#define RK3588_SET_HPD_PATH_MASK GENMASK(13, 12) +#define RK3588_GRF_SOC_STATUS1 0x0384 +#define RK3588_HDMI0_LEVEL_INT BIT(16) +#define RK3588_GRF_VO1_CON3 0x000c +#define RK3588_SCLIN_MASK BIT(9) +#define RK3588_SDAIN_MASK BIT(10) +#define RK3588_MODE_MASK BIT(11) +#define RK3588_I2S_SEL_MASK BIT(13) +#define RK3588_GRF_VO1_CON9 0x0024 +#define RK3588_HDMI0_GRANT_SEL BIT(10) + +#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) + +struct rockchip_hdmi_qp { + struct device *dev; + struct regmap *regmap; + struct regmap *vo_regmap; + struct rockchip_encoder encoder; + struct clk *ref_clk; + struct dw_hdmi_qp *hdmi; + struct phy *phy; + struct gpio_desc *enable_gpio; + struct delayed_work hpd_work; +}; + +static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(struct drm_encoder *encoder) +{ + struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); + + return container_of(rkencoder, struct rockchip_hdmi_qp, encoder); +} + +static void +dw_hdmi_qp_rockchip_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder); + + clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); +} + +static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) +{ + struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder); + struct drm_crtc *crtc = encoder->crtc; + int rate; + + /* Unconditionally switch to TMDS as FRL is not yet supported */ + gpiod_set_value(hdmi->enable_gpio, 1); + + if (crtc && crtc->state) { + clk_set_rate(hdmi->ref_clk, + crtc->state->adjusted_mode.crtc_clock * 1000); + /* + * FIXME: Temporary workaround to pass pixel clock rate + * to the PHY driver until phy_configure_opts_hdmi + * becomes available in the PHY API. See also the related + * comment in rk_hdptx_phy_power_on() from + * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c + */ + rate = crtc->state->mode.clock * 10; + phy_set_bus_width(hdmi->phy, rate); + drm_dbg(hdmi, "%s set bus_width=%u\n", __func__, rate); + } +} + +static int +dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + + s->output_mode = ROCKCHIP_OUT_MODE_AAAA; + s->output_type = DRM_MODE_CONNECTOR_HDMIA; + + return 0; +} + +static const struct +drm_encoder_helper_funcs dw_hdmi_qp_rockchip_encoder_helper_funcs = { + .mode_set = dw_hdmi_qp_rockchip_encoder_mode_set, + .enable = dw_hdmi_qp_rockchip_encoder_enable, + .atomic_check = dw_hdmi_qp_rockchip_encoder_atomic_check, +}; + +static int dw_hdmi_qp_rk3588_phy_init(struct dw_hdmi_qp *dw_hdmi, void *data, + const struct drm_display_info *display) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + + return phy_power_on(hdmi->phy); +} + +static void dw_hdmi_qp_rk3588_phy_disable(struct dw_hdmi_qp *dw_hdmi, + void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + + phy_power_off(hdmi->phy); +} + +static enum drm_connector_status +dw_hdmi_qp_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + u32 val; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val); + + return val & RK3588_HDMI0_LEVEL_INT ? + connector_status_connected : connector_status_disconnected; +} + +static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + + regmap_write(hdmi->regmap, + RK3588_GRF_SOC_CON2, + HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, + RK3588_HDMI0_HPD_INT_CLR | + RK3588_HDMI0_HPD_INT_MSK)); +} + +static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = { + .init = dw_hdmi_qp_rk3588_phy_init, + .disable = dw_hdmi_qp_rk3588_phy_disable, + .read_hpd = dw_hdmi_qp_rk3588_read_hpd, + .setup_hpd = dw_hdmi_qp_rk3588_setup_hpd, +}; + +static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work) +{ + struct rockchip_hdmi_qp *hdmi = container_of(work, + struct rockchip_hdmi_qp, + hpd_work.work); + struct drm_device *drm = hdmi->encoder.encoder.dev; + bool changed; + + if (drm) { + changed = drm_helper_hpd_irq_event(drm); + if (changed) + drm_dbg(hdmi, "connector status changed\n"); + } +} + +static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id) +{ + struct rockchip_hdmi_qp *hdmi = dev_id; + u32 intr_stat, val; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); + + if (intr_stat) { + val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, + RK3588_HDMI0_HPD_INT_MSK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id) +{ + struct rockchip_hdmi_qp *hdmi = dev_id; + u32 intr_stat, val; + int debounce_ms; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); + if (!intr_stat) + return IRQ_NONE; + + val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, + RK3588_HDMI0_HPD_INT_CLR); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + debounce_ms = intr_stat & RK3588_HDMI0_LEVEL_INT ? 150 : 20; + mod_delayed_work(system_wq, &hdmi->hpd_work, + msecs_to_jiffies(debounce_ms)); + + val |= HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + return IRQ_HANDLED; +} + +static const struct of_device_id dw_hdmi_qp_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3588-dw-hdmi-qp", + .data = &rk3588_hdmi_phy_ops }, + {}, +}; +MODULE_DEVICE_TABLE(of, dw_hdmi_qp_rockchip_dt_ids); + +static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master, + void *data) +{ + static const char * const clk_names[] = { + "pclk", "earc", "aud", "hdp", "hclk_vo1", + "ref" /* keep "ref" last */ + }; + struct platform_device *pdev = to_platform_device(dev); + struct dw_hdmi_qp_plat_data plat_data; + struct drm_device *drm = data; + struct drm_connector *connector; + struct drm_encoder *encoder; + struct rockchip_hdmi_qp *hdmi; + struct clk *clk; + int ret, irq, i; + u32 val; + + if (!pdev->dev.of_node) + return -ENODEV; + + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + plat_data.phy_ops = of_device_get_match_data(dev); + if (!plat_data.phy_ops) + return -ENODEV; + + plat_data.phy_data = hdmi; + hdmi->dev = &pdev->dev; + + encoder = &hdmi->encoder.encoder; + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); + + rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, + dev->of_node, 0, 0); + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (encoder->possible_crtcs == 0) + return -EPROBE_DEFER; + + hdmi->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,grf"); + if (IS_ERR(hdmi->regmap)) { + drm_err(hdmi, "Unable to get rockchip,grf\n"); + return PTR_ERR(hdmi->regmap); + } + + hdmi->vo_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,vo-grf"); + if (IS_ERR(hdmi->vo_regmap)) { + drm_err(hdmi, "Unable to get rockchip,vo-grf\n"); + return PTR_ERR(hdmi->vo_regmap); + } + + for (i = 0; i < ARRAY_SIZE(clk_names); i++) { + clk = devm_clk_get_enabled(hdmi->dev, clk_names[i]); + + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + if (ret != -EPROBE_DEFER) + drm_err(hdmi, "Failed to get %s clock: %d\n", + clk_names[i], ret); + return ret; + } + } + hdmi->ref_clk = clk; + + hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable", + GPIOD_OUT_HIGH); + if (IS_ERR(hdmi->enable_gpio)) { + ret = PTR_ERR(hdmi->enable_gpio); + drm_err(hdmi, "Failed to request enable GPIO: %d\n", ret); + return ret; + } + + hdmi->phy = devm_of_phy_get_by_index(dev, dev->of_node, 0); + if (IS_ERR(hdmi->phy)) { + ret = PTR_ERR(hdmi->phy); + if (ret != -EPROBE_DEFER) + drm_err(hdmi, "failed to get phy: %d\n", ret); + return ret; + } + + val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON3, val); + + val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); + + val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, + RK3588_HDMI0_GRANT_SEL); + regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val); + + val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + INIT_DELAYED_WORK(&hdmi->hpd_work, dw_hdmi_qp_rk3588_hpd_work); + + plat_data.main_irq = platform_get_irq_byname(pdev, "main"); + if (plat_data.main_irq < 0) + return plat_data.main_irq; + + irq = platform_get_irq_byname(pdev, "hpd"); + if (irq < 0) + return irq; + + ret = devm_request_threaded_irq(hdmi->dev, irq, + dw_hdmi_qp_rk3588_hardirq, + dw_hdmi_qp_rk3588_irq, + IRQF_SHARED, "dw-hdmi-qp-hpd", + hdmi); + if (ret) + return ret; + + drm_encoder_helper_add(encoder, &dw_hdmi_qp_rockchip_encoder_helper_funcs); + drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); + + platform_set_drvdata(pdev, hdmi); + + hdmi->hdmi = dw_hdmi_qp_bind(pdev, encoder, &plat_data); + if (IS_ERR(hdmi->hdmi)) { + ret = PTR_ERR(hdmi->hdmi); + drm_encoder_cleanup(encoder); + return ret; + } + + connector = drm_bridge_connector_init(drm, encoder); + if (IS_ERR(connector)) { + ret = PTR_ERR(connector); + drm_err(hdmi, "failed to init bridge connector: %d\n", ret); + return ret; + } + + return drm_connector_attach_encoder(connector, encoder); +} + +static void dw_hdmi_qp_rockchip_unbind(struct device *dev, + struct device *master, + void *data) +{ + struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev); + + cancel_delayed_work_sync(&hdmi->hpd_work); + + drm_encoder_cleanup(&hdmi->encoder.encoder); +} + +static const struct component_ops dw_hdmi_qp_rockchip_ops = { + .bind = dw_hdmi_qp_rockchip_bind, + .unbind = dw_hdmi_qp_rockchip_unbind, +}; + +static int dw_hdmi_qp_rockchip_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &dw_hdmi_qp_rockchip_ops); +} + +static void dw_hdmi_qp_rockchip_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &dw_hdmi_qp_rockchip_ops); +} + +static int __maybe_unused dw_hdmi_qp_rockchip_resume(struct device *dev) +{ + struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev); + u32 val; + + val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON3, val); + + val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); + + val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, + RK3588_HDMI0_GRANT_SEL); + regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val); + + dw_hdmi_qp_resume(dev, hdmi->hdmi); + + if (hdmi->encoder.encoder.dev) + drm_helper_hpd_irq_event(hdmi->encoder.encoder.dev); + + return 0; +} + +static const struct dev_pm_ops dw_hdmi_qp_rockchip_pm = { + SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_qp_rockchip_resume) +}; + +struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver = { + .probe = dw_hdmi_qp_rockchip_probe, + .remove_new = dw_hdmi_qp_rockchip_remove, + .driver = { + .name = "dwhdmiqp-rockchip", + .pm = &dw_hdmi_qp_rockchip_pm, + .of_match_table = dw_hdmi_qp_rockchip_dt_ids, + }, +}; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 44d769d9234d..04ef7a2c3833 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -503,6 +503,8 @@ static int __init rockchip_drm_init(void) ADD_ROCKCHIP_SUB_DRIVER(cdn_dp_driver, CONFIG_ROCKCHIP_CDN_DP); ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_rockchip_pltfm_driver, CONFIG_ROCKCHIP_DW_HDMI); + ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_qp_rockchip_pltfm_driver, + CONFIG_ROCKCHIP_DW_HDMI_QP); ADD_ROCKCHIP_SUB_DRIVER(dw_mipi_dsi_rockchip_driver, CONFIG_ROCKCHIP_DW_MIPI_DSI); ADD_ROCKCHIP_SUB_DRIVER(inno_hdmi_driver, CONFIG_ROCKCHIP_INNO_HDMI); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index bbb9e0bf6804..d7f2f0fd02e6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -87,6 +87,7 @@ int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder, int rockchip_drm_endpoint_is_subdriver(struct device_node *ep); extern struct platform_driver cdn_dp_driver; extern struct platform_driver dw_hdmi_rockchip_pltfm_driver; +extern struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver; extern struct platform_driver dw_mipi_dsi_rockchip_driver; extern struct platform_driver inno_hdmi_driver; extern struct platform_driver rockchip_dp_driver;

[v6,3/3] drm/rockchip: Add basic RK3588 HDMI output support

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