| Message ID | 20240909021317.58192-3-alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: char: Avoid dropped charecters | expand |
On 9/8/24 11:13 PM, Alistair Francis wrote: > The current approach of using qemu_chr_fe_write() and ignoring the > return values results in dropped characters [1]. > > Let's update the SiFive UART to use a async sifive_uart_xmit() function > to transmit the characters and apply back pressure to the guest with > the SIFIVE_UART_TXFIFO_FULL status. > > This should avoid dropped characters and more realisticly model the > hardware. > > 1: https://gitlab.com/qemu-project/qemu/-/issues/2114 > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > include/hw/char/sifive_uart.h | 17 ++++++- > hw/char/sifive_uart.c | 88 +++++++++++++++++++++++++++++++++-- > 2 files changed, 99 insertions(+), 6 deletions(-) > > diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h > index 7f6c79f8bd..b43109bb8b 100644 > --- a/include/hw/char/sifive_uart.h > +++ b/include/hw/char/sifive_uart.h > @@ -24,6 +24,7 @@ > #include "hw/qdev-properties.h" > #include "hw/sysbus.h" > #include "qom/object.h" > +#include "qemu/fifo8.h" > > enum { > SIFIVE_UART_TXFIFO = 0, > @@ -48,9 +49,13 @@ enum { > SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ > }; > > +#define SIFIVE_UART_TXFIFO_FULL 0x80000000 > + > #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) > #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) > + > #define SIFIVE_UART_RX_FIFO_SIZE 8 > +#define SIFIVE_UART_TX_FIFO_SIZE 8 > > #define TYPE_SIFIVE_UART "riscv.sifive.uart" > OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART) > @@ -63,13 +68,21 @@ struct SiFiveUARTState { > qemu_irq irq; > MemoryRegion mmio; > CharBackend chr; > - uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; > - uint8_t rx_fifo_len; > + > + uint32_t txfifo; > uint32_t ie; > uint32_t ip; > uint32_t txctrl; > uint32_t rxctrl; > uint32_t div; > + > + uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; > + uint8_t rx_fifo_len; > + > + Fifo8 tx_fifo; > + > + QEMUTimer *fifo_trigger_handle; > + uint64_t char_tx_time; > }; > > SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, > diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c > index 7fc6787f69..ab899b60d6 100644 > --- a/hw/char/sifive_uart.c > +++ b/hw/char/sifive_uart.c > @@ -64,6 +64,72 @@ static void sifive_uart_update_irq(SiFiveUARTState *s) > } > } > > +static gboolean sifive_uart_xmit(void *do_not_use, GIOCondition cond, > + void *opaque) > +{ > + SiFiveUARTState *s = opaque; > + int ret; > + const uint8_t *charecters; > + uint32_t numptr = 0; > + > + /* instant drain the fifo when there's no back-end */ > + if (!qemu_chr_fe_backend_connected(&s->chr)) { > + fifo8_reset(&s->tx_fifo); > + return G_SOURCE_REMOVE; > + } > + > + if (fifo8_is_empty(&s->tx_fifo)) { > + return G_SOURCE_REMOVE; > + } > + > + /* Don't pop the FIFO in case the write fails */ > + charecters = fifo8_peek_bufptr(&s->tx_fifo, > + fifo8_num_used(&s->tx_fifo), &numptr); > + ret = qemu_chr_fe_write(&s->chr, charecters, numptr); > + > + if (ret >= 0) { > + /* We wrote the data, actually pop the fifo */ > + fifo8_pop_bufptr(&s->tx_fifo, ret, NULL); > + } > + > + if (!fifo8_is_empty(&s->tx_fifo)) { > + guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, > + sifive_uart_xmit, s); > + if (!r) { > + fifo8_reset(&s->tx_fifo); > + return G_SOURCE_REMOVE; > + } > + } > + > + /* Clear the TX Full bit */ > + if (!fifo8_is_full(&s->tx_fifo)) { > + s->txfifo &= ~SIFIVE_UART_TXFIFO_FULL; > + } > + > + sifive_uart_update_irq(s); > + return G_SOURCE_REMOVE; > +} > + > +static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *buf, > + int size) > +{ > + uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + > + if (size > fifo8_num_free(&s->tx_fifo)) { > + size = fifo8_num_free(&s->tx_fifo); > + qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow"); > + } > + > + fifo8_push_all(&s->tx_fifo, buf, size); > + > + if (fifo8_is_full(&s->tx_fifo)) { > + s->txfifo |= SIFIVE_UART_TXFIFO_FULL; > + } > + > + timer_mod(s->fifo_trigger_handle, current_time + > + (s->char_tx_time * 4)); > +} > + > static uint64_t > sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) > { > @@ -82,7 +148,7 @@ sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) > return 0x80000000; > > case SIFIVE_UART_TXFIFO: > - return 0; /* Should check tx fifo */ > + return s->txfifo; > case SIFIVE_UART_IE: > return s->ie; > case SIFIVE_UART_IP: > @@ -106,12 +172,10 @@ sifive_uart_write(void *opaque, hwaddr addr, > { > SiFiveUARTState *s = opaque; > uint32_t value = val64; > - unsigned char ch = value; > > switch (addr) { > case SIFIVE_UART_TXFIFO: > - qemu_chr_fe_write(&s->chr, &ch, 1); > - sifive_uart_update_irq(s); > + sifive_uart_write_tx_fifo(s, (uint8_t *) &value, 1); > return; > case SIFIVE_UART_IE: > s->ie = val64; > @@ -131,6 +195,13 @@ sifive_uart_write(void *opaque, hwaddr addr, > __func__, (int)addr, (int)value); > } > > +static void fifo_trigger_update(void *opaque) > +{ > + SiFiveUARTState *s = opaque; > + > + sifive_uart_xmit(NULL, G_IO_OUT, s); > +} > + > static const MemoryRegionOps sifive_uart_ops = { > .read = sifive_uart_read, > .write = sifive_uart_write, > @@ -197,6 +268,9 @@ static void sifive_uart_realize(DeviceState *dev, Error **errp) > { > SiFiveUARTState *s = SIFIVE_UART(dev); > > + s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, > + fifo_trigger_update, s); > + > qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, > sifive_uart_event, sifive_uart_be_change, s, > NULL, true); > @@ -206,12 +280,18 @@ static void sifive_uart_realize(DeviceState *dev, Error **errp) > static void sifive_uart_reset_enter(Object *obj, ResetType type) > { > SiFiveUARTState *s = SIFIVE_UART(obj); > + > + s->txfifo = 0; > s->ie = 0; > s->ip = 0; > s->txctrl = 0; > s->rxctrl = 0; > s->div = 0; > + > s->rx_fifo_len = 0; > + > + memset(s->rx_fifo, 0, SIFIVE_UART_RX_FIFO_SIZE); > + fifo8_create(&s->tx_fifo, SIFIVE_UART_TX_FIFO_SIZE); > } > > static void sifive_uart_reset_hold(Object *obj, ResetType type)
Hi Alistair, On 9/9/24 04:13, Alistair Francis wrote: > The current approach of using qemu_chr_fe_write() and ignoring the > return values results in dropped characters [1]. > > Let's update the SiFive UART to use a async sifive_uart_xmit() function > to transmit the characters and apply back pressure to the guest with > the SIFIVE_UART_TXFIFO_FULL status. > > This should avoid dropped characters and more realisticly model the > hardware. > > 1: https://gitlab.com/qemu-project/qemu/-/issues/2114 > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > Tested-by: Thomas Huth <thuth@redhat.com> > --- > include/hw/char/sifive_uart.h | 17 ++++++- > hw/char/sifive_uart.c | 88 +++++++++++++++++++++++++++++++++-- > 2 files changed, 99 insertions(+), 6 deletions(-) > > diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h > index 7f6c79f8bd..b43109bb8b 100644 > --- a/include/hw/char/sifive_uart.h > +++ b/include/hw/char/sifive_uart.h > @@ -24,6 +24,7 @@ > #include "hw/qdev-properties.h" > #include "hw/sysbus.h" > #include "qom/object.h" > +#include "qemu/fifo8.h" > > enum { > SIFIVE_UART_TXFIFO = 0, > @@ -48,9 +49,13 @@ enum { > SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ > }; > > +#define SIFIVE_UART_TXFIFO_FULL 0x80000000 > + > #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) > #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) > + > #define SIFIVE_UART_RX_FIFO_SIZE 8 > +#define SIFIVE_UART_TX_FIFO_SIZE 8 > > #define TYPE_SIFIVE_UART "riscv.sifive.uart" > OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART) > @@ -63,13 +68,21 @@ struct SiFiveUARTState { > qemu_irq irq; > MemoryRegion mmio; > CharBackend chr; > - uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; > - uint8_t rx_fifo_len; > + > + uint32_t txfifo; > uint32_t ie; > uint32_t ip; > uint32_t txctrl; > uint32_t rxctrl; > uint32_t div; > + > + uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; > + uint8_t rx_fifo_len; > + > + Fifo8 tx_fifo; > + > + QEMUTimer *fifo_trigger_handle; > + uint64_t char_tx_time; Unfortunately some fields now need to be migrated and tracked in vmstate_sifive_uart[]. > }; > > SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, > diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c > index 7fc6787f69..ab899b60d6 100644 > --- a/hw/char/sifive_uart.c > +++ b/hw/char/sifive_uart.c > @@ -64,6 +64,72 @@ static void sifive_uart_update_irq(SiFiveUARTState *s) > } > } > > +static gboolean sifive_uart_xmit(void *do_not_use, GIOCondition cond, > + void *opaque) > +{ > + SiFiveUARTState *s = opaque; > + int ret; > + const uint8_t *charecters; "characters" ;) > + uint32_t numptr = 0; > + > + /* instant drain the fifo when there's no back-end */ > + if (!qemu_chr_fe_backend_connected(&s->chr)) { > + fifo8_reset(&s->tx_fifo); > + return G_SOURCE_REMOVE; > + } > + > + if (fifo8_is_empty(&s->tx_fifo)) { > + return G_SOURCE_REMOVE; > + } > + > + /* Don't pop the FIFO in case the write fails */ > + charecters = fifo8_peek_bufptr(&s->tx_fifo, > + fifo8_num_used(&s->tx_fifo), &numptr); > + ret = qemu_chr_fe_write(&s->chr, charecters, numptr); > + > + if (ret >= 0) { > + /* We wrote the data, actually pop the fifo */ > + fifo8_pop_bufptr(&s->tx_fifo, ret, NULL); > + } > + > + if (!fifo8_is_empty(&s->tx_fifo)) { > + guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, > + sifive_uart_xmit, s); > + if (!r) { > + fifo8_reset(&s->tx_fifo); > + return G_SOURCE_REMOVE; > + } > + } > + > + /* Clear the TX Full bit */ > + if (!fifo8_is_full(&s->tx_fifo)) { > + s->txfifo &= ~SIFIVE_UART_TXFIFO_FULL; > + } > + > + sifive_uart_update_irq(s); > + return G_SOURCE_REMOVE; Alex suggested to see if we can have a generic (abstract?) FIFO char implementation. I might have a look later when I get the PL011 series in. > +} > + > +static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *buf, > + int size) > +{ > + uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + > + if (size > fifo8_num_free(&s->tx_fifo)) { > + size = fifo8_num_free(&s->tx_fifo); > + qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow"); > + } > + > + fifo8_push_all(&s->tx_fifo, buf, size); > + > + if (fifo8_is_full(&s->tx_fifo)) { > + s->txfifo |= SIFIVE_UART_TXFIFO_FULL; > + } > + > + timer_mod(s->fifo_trigger_handle, current_time + > + (s->char_tx_time * 4)); > +} > + > static uint64_t > sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) > { > @@ -82,7 +148,7 @@ sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) > return 0x80000000; > > case SIFIVE_UART_TXFIFO: > - return 0; /* Should check tx fifo */ > + return s->txfifo; > case SIFIVE_UART_IE: > return s->ie; > case SIFIVE_UART_IP: > @@ -106,12 +172,10 @@ sifive_uart_write(void *opaque, hwaddr addr, > { > SiFiveUARTState *s = opaque; > uint32_t value = val64; > - unsigned char ch = value; > > switch (addr) { > case SIFIVE_UART_TXFIFO: > - qemu_chr_fe_write(&s->chr, &ch, 1); > - sifive_uart_update_irq(s); > + sifive_uart_write_tx_fifo(s, (uint8_t *) &value, 1); > return; > case SIFIVE_UART_IE: > s->ie = val64; > @@ -131,6 +195,13 @@ sifive_uart_write(void *opaque, hwaddr addr, > __func__, (int)addr, (int)value); > } > > +static void fifo_trigger_update(void *opaque) > +{ > + SiFiveUARTState *s = opaque; > + > + sifive_uart_xmit(NULL, G_IO_OUT, s); > +} > + > static const MemoryRegionOps sifive_uart_ops = { > .read = sifive_uart_read, > .write = sifive_uart_write, > @@ -197,6 +268,9 @@ static void sifive_uart_realize(DeviceState *dev, Error **errp) > { > SiFiveUARTState *s = SIFIVE_UART(dev); > > + s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, > + fifo_trigger_update, s); > + > qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, > sifive_uart_event, sifive_uart_be_change, s, > NULL, true); > @@ -206,12 +280,18 @@ static void sifive_uart_realize(DeviceState *dev, Error **errp) > static void sifive_uart_reset_enter(Object *obj, ResetType type) > { > SiFiveUARTState *s = SIFIVE_UART(obj); > + > + s->txfifo = 0; > s->ie = 0; > s->ip = 0; > s->txctrl = 0; > s->rxctrl = 0; > s->div = 0; > + > s->rx_fifo_len = 0; > + > + memset(s->rx_fifo, 0, SIFIVE_UART_RX_FIFO_SIZE); > + fifo8_create(&s->tx_fifo, SIFIVE_UART_TX_FIFO_SIZE); > } > > static void sifive_uart_reset_hold(Object *obj, ResetType type)
Hi Alistair, On 9/9/24 04:13, Alistair Francis wrote: > The current approach of using qemu_chr_fe_write() and ignoring the > return values results in dropped characters [1]. > > Let's update the SiFive UART to use a async sifive_uart_xmit() function > to transmit the characters and apply back pressure to the guest with > the SIFIVE_UART_TXFIFO_FULL status. > > This should avoid dropped characters and more realisticly model the > hardware. > > 1: https://gitlab.com/qemu-project/qemu/-/issues/2114 > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > Tested-by: Thomas Huth <thuth@redhat.com> > --- > include/hw/char/sifive_uart.h | 17 ++++++- > hw/char/sifive_uart.c | 88 +++++++++++++++++++++++++++++++++-- > 2 files changed, 99 insertions(+), 6 deletions(-) > > diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h > index 7f6c79f8bd..b43109bb8b 100644 > --- a/include/hw/char/sifive_uart.h > +++ b/include/hw/char/sifive_uart.h > @@ -24,6 +24,7 @@ > #include "hw/qdev-properties.h" > #include "hw/sysbus.h" > #include "qom/object.h" > +#include "qemu/fifo8.h" > > enum { > SIFIVE_UART_TXFIFO = 0, > @@ -48,9 +49,13 @@ enum { > SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ > }; > > +#define SIFIVE_UART_TXFIFO_FULL 0x80000000 > + > #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) > #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) > + > #define SIFIVE_UART_RX_FIFO_SIZE 8 > +#define SIFIVE_UART_TX_FIFO_SIZE 8 > > #define TYPE_SIFIVE_UART "riscv.sifive.uart" > OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART) > @@ -63,13 +68,21 @@ struct SiFiveUARTState { > qemu_irq irq; > MemoryRegion mmio; > CharBackend chr; > - uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; > - uint8_t rx_fifo_len; > + > + uint32_t txfifo; > uint32_t ie; > uint32_t ip; > uint32_t txctrl; > uint32_t rxctrl; > uint32_t div; > + > + uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; > + uint8_t rx_fifo_len; > + > + Fifo8 tx_fifo; > + > + QEMUTimer *fifo_trigger_handle; > + uint64_t char_tx_time; Unfortunately some fields now need to be migrated and tracked in vmstate_sifive_uart[]. > }; > > SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, > diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c > index 7fc6787f69..ab899b60d6 100644 > --- a/hw/char/sifive_uart.c > +++ b/hw/char/sifive_uart.c > @@ -64,6 +64,72 @@ static void sifive_uart_update_irq(SiFiveUARTState *s) > } > } > > +static gboolean sifive_uart_xmit(void *do_not_use, GIOCondition cond, > + void *opaque) > +{ > + SiFiveUARTState *s = opaque; > + int ret; > + const uint8_t *charecters; "characters" ;) > + uint32_t numptr = 0; > + > + /* instant drain the fifo when there's no back-end */ > + if (!qemu_chr_fe_backend_connected(&s->chr)) { > + fifo8_reset(&s->tx_fifo); > + return G_SOURCE_REMOVE; > + } > + > + if (fifo8_is_empty(&s->tx_fifo)) { > + return G_SOURCE_REMOVE; > + } > + > + /* Don't pop the FIFO in case the write fails */ > + charecters = fifo8_peek_bufptr(&s->tx_fifo, > + fifo8_num_used(&s->tx_fifo), &numptr); > + ret = qemu_chr_fe_write(&s->chr, charecters, numptr); > + > + if (ret >= 0) { > + /* We wrote the data, actually pop the fifo */ > + fifo8_pop_bufptr(&s->tx_fifo, ret, NULL); > + } > + > + if (!fifo8_is_empty(&s->tx_fifo)) { > + guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, > + sifive_uart_xmit, s); > + if (!r) { > + fifo8_reset(&s->tx_fifo); > + return G_SOURCE_REMOVE; > + } > + } > + > + /* Clear the TX Full bit */ > + if (!fifo8_is_full(&s->tx_fifo)) { > + s->txfifo &= ~SIFIVE_UART_TXFIFO_FULL; > + } > + > + sifive_uart_update_irq(s); > + return G_SOURCE_REMOVE; Alex suggested to see if we can have a generic (abstract?) FIFO char implementation. I might have a look later when I get the PL011 series in. > +} > + > +static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *buf, > + int size) > +{ > + uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + > + if (size > fifo8_num_free(&s->tx_fifo)) { > + size = fifo8_num_free(&s->tx_fifo); > + qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow"); > + } > + > + fifo8_push_all(&s->tx_fifo, buf, size); > + > + if (fifo8_is_full(&s->tx_fifo)) { > + s->txfifo |= SIFIVE_UART_TXFIFO_FULL; > + } > + > + timer_mod(s->fifo_trigger_handle, current_time + > + (s->char_tx_time * 4)); > +} > + > static uint64_t > sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) > { > @@ -82,7 +148,7 @@ sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) > return 0x80000000; > > case SIFIVE_UART_TXFIFO: > - return 0; /* Should check tx fifo */ > + return s->txfifo; > case SIFIVE_UART_IE: > return s->ie; > case SIFIVE_UART_IP: > @@ -106,12 +172,10 @@ sifive_uart_write(void *opaque, hwaddr addr, > { > SiFiveUARTState *s = opaque; > uint32_t value = val64; > - unsigned char ch = value; > > switch (addr) { > case SIFIVE_UART_TXFIFO: > - qemu_chr_fe_write(&s->chr, &ch, 1); > - sifive_uart_update_irq(s); > + sifive_uart_write_tx_fifo(s, (uint8_t *) &value, 1); > return; > case SIFIVE_UART_IE: > s->ie = val64; > @@ -131,6 +195,13 @@ sifive_uart_write(void *opaque, hwaddr addr, > __func__, (int)addr, (int)value); > } > > +static void fifo_trigger_update(void *opaque) > +{ > + SiFiveUARTState *s = opaque; > + > + sifive_uart_xmit(NULL, G_IO_OUT, s); > +} > + > static const MemoryRegionOps sifive_uart_ops = { > .read = sifive_uart_read, > .write = sifive_uart_write, > @@ -197,6 +268,9 @@ static void sifive_uart_realize(DeviceState *dev, Error **errp) > { > SiFiveUARTState *s = SIFIVE_UART(dev); > > + s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, > + fifo_trigger_update, s); > + > qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, > sifive_uart_event, sifive_uart_be_change, s, > NULL, true); > @@ -206,12 +280,18 @@ static void sifive_uart_realize(DeviceState *dev, Error **errp) > static void sifive_uart_reset_enter(Object *obj, ResetType type) > { > SiFiveUARTState *s = SIFIVE_UART(obj); > + > + s->txfifo = 0; > s->ie = 0; > s->ip = 0; > s->txctrl = 0; > s->rxctrl = 0; > s->div = 0; > + > s->rx_fifo_len = 0; > + > + memset(s->rx_fifo, 0, SIFIVE_UART_RX_FIFO_SIZE); > + fifo8_create(&s->tx_fifo, SIFIVE_UART_TX_FIFO_SIZE); > } > > static void sifive_uart_reset_hold(Object *obj, ResetType type)
diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h index 7f6c79f8bd..b43109bb8b 100644 --- a/include/hw/char/sifive_uart.h +++ b/include/hw/char/sifive_uart.h @@ -24,6 +24,7 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qom/object.h" +#include "qemu/fifo8.h" enum { SIFIVE_UART_TXFIFO = 0, @@ -48,9 +49,13 @@ enum { SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ }; +#define SIFIVE_UART_TXFIFO_FULL 0x80000000 + #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) + #define SIFIVE_UART_RX_FIFO_SIZE 8 +#define SIFIVE_UART_TX_FIFO_SIZE 8 #define TYPE_SIFIVE_UART "riscv.sifive.uart" OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART) @@ -63,13 +68,21 @@ struct SiFiveUARTState { qemu_irq irq; MemoryRegion mmio; CharBackend chr; - uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; - uint8_t rx_fifo_len; + + uint32_t txfifo; uint32_t ie; uint32_t ip; uint32_t txctrl; uint32_t rxctrl; uint32_t div; + + uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; + uint8_t rx_fifo_len; + + Fifo8 tx_fifo; + + QEMUTimer *fifo_trigger_handle; + uint64_t char_tx_time; }; SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 7fc6787f69..ab899b60d6 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -64,6 +64,72 @@ static void sifive_uart_update_irq(SiFiveUARTState *s) } } +static gboolean sifive_uart_xmit(void *do_not_use, GIOCondition cond, + void *opaque) +{ + SiFiveUARTState *s = opaque; + int ret; + const uint8_t *charecters; + uint32_t numptr = 0; + + /* instant drain the fifo when there's no back-end */ + if (!qemu_chr_fe_backend_connected(&s->chr)) { + fifo8_reset(&s->tx_fifo); + return G_SOURCE_REMOVE; + } + + if (fifo8_is_empty(&s->tx_fifo)) { + return G_SOURCE_REMOVE; + } + + /* Don't pop the FIFO in case the write fails */ + charecters = fifo8_peek_bufptr(&s->tx_fifo, + fifo8_num_used(&s->tx_fifo), &numptr); + ret = qemu_chr_fe_write(&s->chr, charecters, numptr); + + if (ret >= 0) { + /* We wrote the data, actually pop the fifo */ + fifo8_pop_bufptr(&s->tx_fifo, ret, NULL); + } + + if (!fifo8_is_empty(&s->tx_fifo)) { + guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, + sifive_uart_xmit, s); + if (!r) { + fifo8_reset(&s->tx_fifo); + return G_SOURCE_REMOVE; + } + } + + /* Clear the TX Full bit */ + if (!fifo8_is_full(&s->tx_fifo)) { + s->txfifo &= ~SIFIVE_UART_TXFIFO_FULL; + } + + sifive_uart_update_irq(s); + return G_SOURCE_REMOVE; +} + +static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *buf, + int size) +{ + uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + if (size > fifo8_num_free(&s->tx_fifo)) { + size = fifo8_num_free(&s->tx_fifo); + qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow"); + } + + fifo8_push_all(&s->tx_fifo, buf, size); + + if (fifo8_is_full(&s->tx_fifo)) { + s->txfifo |= SIFIVE_UART_TXFIFO_FULL; + } + + timer_mod(s->fifo_trigger_handle, current_time + + (s->char_tx_time * 4)); +} + static uint64_t sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) { @@ -82,7 +148,7 @@ sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) return 0x80000000; case SIFIVE_UART_TXFIFO: - return 0; /* Should check tx fifo */ + return s->txfifo; case SIFIVE_UART_IE: return s->ie; case SIFIVE_UART_IP: @@ -106,12 +172,10 @@ sifive_uart_write(void *opaque, hwaddr addr, { SiFiveUARTState *s = opaque; uint32_t value = val64; - unsigned char ch = value; switch (addr) { case SIFIVE_UART_TXFIFO: - qemu_chr_fe_write(&s->chr, &ch, 1); - sifive_uart_update_irq(s); + sifive_uart_write_tx_fifo(s, (uint8_t *) &value, 1); return; case SIFIVE_UART_IE: s->ie = val64; @@ -131,6 +195,13 @@ sifive_uart_write(void *opaque, hwaddr addr, __func__, (int)addr, (int)value); } +static void fifo_trigger_update(void *opaque) +{ + SiFiveUARTState *s = opaque; + + sifive_uart_xmit(NULL, G_IO_OUT, s); +} + static const MemoryRegionOps sifive_uart_ops = { .read = sifive_uart_read, .write = sifive_uart_write, @@ -197,6 +268,9 @@ static void sifive_uart_realize(DeviceState *dev, Error **errp) { SiFiveUARTState *s = SIFIVE_UART(dev); + s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, + fifo_trigger_update, s); + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, sifive_uart_event, sifive_uart_be_change, s, NULL, true); @@ -206,12 +280,18 @@ static void sifive_uart_realize(DeviceState *dev, Error **errp) static void sifive_uart_reset_enter(Object *obj, ResetType type) { SiFiveUARTState *s = SIFIVE_UART(obj); + + s->txfifo = 0; s->ie = 0; s->ip = 0; s->txctrl = 0; s->rxctrl = 0; s->div = 0; + s->rx_fifo_len = 0; + + memset(s->rx_fifo, 0, SIFIVE_UART_RX_FIFO_SIZE); + fifo8_create(&s->tx_fifo, SIFIVE_UART_TX_FIFO_SIZE); } static void sifive_uart_reset_hold(Object *obj, ResetType type)