diff mbox series

[v1,5/5] xen/arm: Enable workaround for Cortex-A53 erratum #1530924

Message ID 20240910143411.178704-6-andrei.cherechesu@oss.nxp.com (mailing list archive)
State New
Headers show
Series xen/arm: Add support for S32CC platforms and LINFlexD UART | expand

Commit Message

Andrei Cherechesu Sept. 10, 2024, 2:34 p.m. UTC 
From: Andrei Cherechesu <andrei.cherechesu@nxp.com>

All versions of Cortex-A53 cores are affected by the speculative
AT instruction erratum, as mentioned in the Cortex-A53 Revision r0
SDEN v21 documentation.

Enabled ARM64_WORKAROUND_AT_SPECULATE for all versions of Cortex-A53
cores, to avoid corrupting the TLB if performing a speculative AT
instruction during a guest context switch.

Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
---
 docs/misc/arm/silicon-errata.txt | 1 +
 xen/arch/arm/cpuerrata.c         | 6 ++++++
 2 files changed, 7 insertions(+)

Comments

Julien Grall Sept. 11, 2024, 9:17 a.m. UTC | #1 
Hi,

On 10/09/2024 15:34, Andrei Cherechesu (OSS) wrote:
> From: Andrei Cherechesu <andrei.cherechesu@nxp.com>
> 
> All versions of Cortex-A53 cores are affected by the speculative
> AT instruction erratum, as mentioned in the Cortex-A53 Revision r0
> SDEN v21 documentation.
> 
> Enabled ARM64_WORKAROUND_AT_SPECULATE for all versions of Cortex-A53
> cores, to avoid corrupting the TLB if performing a speculative AT
> instruction during a guest context switch.
> 
> Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>

Acked-by: Julien Grall <jgrall@amazon.com>

Cheers,
Julien Grall Sept. 16, 2024, 9:01 p.m. UTC | #2 
Hi,

On 11/09/2024 10:17, Julien Grall wrote:
> On 10/09/2024 15:34, Andrei Cherechesu (OSS) wrote:
>> From: Andrei Cherechesu <andrei.cherechesu@nxp.com>
>>
>> All versions of Cortex-A53 cores are affected by the speculative
>> AT instruction erratum, as mentioned in the Cortex-A53 Revision r0
>> SDEN v21 documentation.
>>
>> Enabled ARM64_WORKAROUND_AT_SPECULATE for all versions of Cortex-A53
>> cores, to avoid corrupting the TLB if performing a speculative AT
>> instruction during a guest context switch.
>>
>> Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
> 
> Acked-by: Julien Grall <jgrall@amazon.com>

I have committed this patch.

Cheers,
diff mbox series

Patch

diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
index fffca09656..853e06aec1 100644
--- a/docs/misc/arm/silicon-errata.txt
+++ b/docs/misc/arm/silicon-errata.txt
@@ -46,6 +46,7 @@  stable hypervisors.
 | ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069    |
 | ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472    |
 | ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419    |
+| ARM            | Cortex-A53      | #1530924        | N/A                     |
 | ARM            | Cortex-A55      | #1530923        | N/A                     |
 | ARM            | Cortex-A57      | #852523         | N/A                     |
 | ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    |
diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index 2b7101ea25..afd0605922 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -683,6 +683,12 @@  static const struct arm_cpu_capabilities arm_errata[] = {
         .capability = ARM64_WORKAROUND_AT_SPECULATE,
         MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
     },
+    {
+        /* Cortex-A53 (All versions) */
+        .desc = "ARM erratum 1530924",
+        .capability = ARM64_WORKAROUND_AT_SPECULATE,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
+    },
     {},
 };