| Message ID | trinity-0e61ef5a-b461-485b-a7ea-787ffe9b1689-1726083054223@3c-app-gmx-bs04 (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: tn40xx: add support for AQR105 based cards (was: net: phy: aquantia: emable firmware loading for aqr105) | expand |
On Wed, 11 Sep 2024 21:30:54 +0200 Hans-Frieder Vogt <hfdevel@gmx.net> wrote: > Prepare the tn40xx driver to load for Tehuti TN9510 cards > and set bit 3 in the TN40_REG_MDIO_CMD_STAT register, because otherwise the > AQR105 PHY will not be found. The function of bit 3 is unclear, but may have > something to do with the length of the preamble in MDIO communication. > > Signed-off-by: Hans-Frieder Vogt <hfdevel@gmx.net> > --- > drivers/net/ethernet/tehuti/tn40.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/net/ethernet/tehuti/tn40.c b/drivers/net/ethernet/tehuti/tn40.c > index 259bdac24cf2..4e6f2f781ffc 100644 > --- a/drivers/net/ethernet/tehuti/tn40.c > +++ b/drivers/net/ethernet/tehuti/tn40.c > @@ -1760,6 +1760,9 @@ static int tn40_probe(struct pci_dev *pdev, const struct pci_device_id *ent) > goto err_unset_drvdata; > } > > + /* essential for identification of some PHYs is bit 3 set */ > + ret = tn40_read_reg(priv, TN40_REG_MDIO_CMD_STAT); > + tn40_write_reg(priv, TN40_REG_MDIO_CMD_STAT, ret | 0x8); > ret = tn40_mdiobus_init(priv); How about setting the speed of mdio 1MHZ by calling tn40_mdio_set_speed() like the vendor driver? The following works for my TN9510 card. diff --git a/drivers/net/ethernet/tehuti/tn40_mdio.c b/drivers/net/ethernet/tehuti/tn40_mdio.c index bbd95fabbea0..e8b8dea250f2 100644 --- a/drivers/net/ethernet/tehuti/tn40_mdio.c +++ b/drivers/net/ethernet/tehuti/tn40_mdio.c @@ -183,6 +183,7 @@ int tn40_mdiobus_init(struct tn40_priv *priv) ret); } + tn40_mdio_set_speed(priv, TN40_MDIO_SPEED_1MHZ); ret = devm_mdiobus_register(&pdev->dev, bus); if (ret) { dev_err(&pdev->dev, "failed to register mdiobus %d %u %u\n",
On 13.09.2024 09.24, FUJITA Tomonori wrote: > On Wed, 11 Sep 2024 21:30:54 +0200 > Hans-Frieder Vogt <hfdevel@gmx.net> wrote: > >> Prepare the tn40xx driver to load for Tehuti TN9510 cards >> and set bit 3 in the TN40_REG_MDIO_CMD_STAT register, because otherwise the >> AQR105 PHY will not be found. The function of bit 3 is unclear, but may have >> something to do with the length of the preamble in MDIO communication. >> >> Signed-off-by: Hans-Frieder Vogt <hfdevel@gmx.net> >> --- >> drivers/net/ethernet/tehuti/tn40.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/net/ethernet/tehuti/tn40.c b/drivers/net/ethernet/tehuti/tn40.c >> index 259bdac24cf2..4e6f2f781ffc 100644 >> --- a/drivers/net/ethernet/tehuti/tn40.c >> +++ b/drivers/net/ethernet/tehuti/tn40.c >> @@ -1760,6 +1760,9 @@ static int tn40_probe(struct pci_dev *pdev, const struct pci_device_id *ent) >> goto err_unset_drvdata; >> } >> >> + /* essential for identification of some PHYs is bit 3 set */ >> + ret = tn40_read_reg(priv, TN40_REG_MDIO_CMD_STAT); >> + tn40_write_reg(priv, TN40_REG_MDIO_CMD_STAT, ret | 0x8); >> ret = tn40_mdiobus_init(priv); > How about setting the speed of mdio 1MHZ by calling > tn40_mdio_set_speed() like the vendor driver? it is not about setting the speed here, but ensuring that bit 3 is set. But I agree, with tn40_mdio_set_speed() the intended effect is also achieved, and will make the code more readable. And my fear to overwrite other bits in this register is also not justified, because the initial value of the register is consistently 0x3ec0. > > The following works for my TN9510 card. > > diff --git a/drivers/net/ethernet/tehuti/tn40_mdio.c b/drivers/net/ethernet/tehuti/tn40_mdio.c > index bbd95fabbea0..e8b8dea250f2 100644 > --- a/drivers/net/ethernet/tehuti/tn40_mdio.c > +++ b/drivers/net/ethernet/tehuti/tn40_mdio.c > @@ -183,6 +183,7 @@ int tn40_mdiobus_init(struct tn40_priv *priv) > ret); > } > > + tn40_mdio_set_speed(priv, TN40_MDIO_SPEED_1MHZ); > ret = devm_mdiobus_register(&pdev->dev, bus); > if (ret) { > dev_err(&pdev->dev, "failed to register mdiobus %d %u %u\n", Yes, of course it can be moved here. Will change it in the next version of the patch. Thanks! Hans
diff --git a/drivers/net/ethernet/tehuti/tn40.c b/drivers/net/ethernet/tehuti/tn40.c index 259bdac24cf2..4e6f2f781ffc 100644 --- a/drivers/net/ethernet/tehuti/tn40.c +++ b/drivers/net/ethernet/tehuti/tn40.c @@ -1760,6 +1760,9 @@ static int tn40_probe(struct pci_dev *pdev, const struct pci_device_id *ent) goto err_unset_drvdata; } + /* essential for identification of some PHYs is bit 3 set */ + ret = tn40_read_reg(priv, TN40_REG_MDIO_CMD_STAT); + tn40_write_reg(priv, TN40_REG_MDIO_CMD_STAT, ret | 0x8); ret = tn40_mdiobus_init(priv); if (ret) { dev_err(&pdev->dev, "failed to initialize mdio bus.\n"); @@ -1832,6 +1835,7 @@ static const struct pci_device_id tn40_id_table[] = { PCI_VENDOR_ID_ASUSTEK, 0x8709) }, { PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022, PCI_VENDOR_ID_EDIMAX, 0x8103) }, + { PCI_VDEVICE(TEHUTI, 0x4025), 0 }, { } };
Prepare the tn40xx driver to load for Tehuti TN9510 cards and set bit 3 in the TN40_REG_MDIO_CMD_STAT register, because otherwise the AQR105 PHY will not be found. The function of bit 3 is unclear, but may have something to do with the length of the preamble in MDIO communication. Signed-off-by: Hans-Frieder Vogt <hfdevel@gmx.net> --- drivers/net/ethernet/tehuti/tn40.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.45.2