| Message ID | 20240911213537.2338164-2-superm1@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/amd/display: Use drm_edid for more code | expand |
Hi Mario, kernel test robot noticed the following build warnings: [auto build test WARNING on amd-pstate/linux-next] [also build test WARNING on amd-pstate/bleeding-edge linus/master v6.11-rc7 next-20240913] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Mario-Limonciello/drm-amd-display-switch-amdgpu_dm_connector-to-use-struct-drm_edid/20240912-093827 base: https://git.kernel.org/pub/scm/linux/kernel/git/superm1/linux.git linux-next patch link: https://lore.kernel.org/r/20240911213537.2338164-2-superm1%40kernel.org patch subject: [PATCH v6 01/10] drm/amd/display: switch amdgpu_dm_connector to use struct drm_edid config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20240915/202409151547.hCDVOK5L-lkp@intel.com/config) compiler: alpha-linux-gcc (GCC) 13.3.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240915/202409151547.hCDVOK5L-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202409151547.hCDVOK5L-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:11976: warning: Function parameter or struct member 'drm_edid' not described in 'amdgpu_dm_update_freesync_caps' >> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:11976: warning: Excess function parameter 'edid' description in 'amdgpu_dm_update_freesync_caps' vim +11976 drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c f9b4f20c4777bd Stylon Wang 2020-12-04 11962 c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11963 /** c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11964 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11965 * 41ee1f18ef5239 Alex Deucher 2022-08-30 11966 * @connector: Connector to query. 41ee1f18ef5239 Alex Deucher 2022-08-30 11967 * @edid: EDID from monitor c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11968 * c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11969 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11970 * track of some of the display information in the internal data struct used by c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11971 * amdgpu_dm. This function checks which type of connector we need to set the c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11972 * FreeSync parameters. c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11973 */ 98e6436d3af5fe Anthony Koo 2018-08-21 11974 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, c8133532d2e08c Melissa Wen 2024-09-11 11975 const struct drm_edid *drm_edid) e7b07ceef2a650 Harry Wentland 2017-08-10 @11976 { eb0709ba077a21 Souptick Joarder 2021-02-23 11977 int i = 0; c8133532d2e08c Melissa Wen 2024-09-11 11978 const struct detailed_timing *timing; c8133532d2e08c Melissa Wen 2024-09-11 11979 const struct detailed_non_pixel *data; c8133532d2e08c Melissa Wen 2024-09-11 11980 const struct detailed_data_monitor_range *range; c84dec2fe8837f Harry Wentland 2017-09-05 11981 struct amdgpu_dm_connector *amdgpu_dm_connector = c84dec2fe8837f Harry Wentland 2017-09-05 11982 to_amdgpu_dm_connector(connector); bb47de73666188 Nicholas Kazlauskas 2018-10-04 11983 struct dm_connector_state *dm_con_state = NULL; 9ad544670514e2 Colin Ian King 2021-08-29 11984 struct dc_sink *sink; 534eee82356c22 Srinivasan Shanmugam 2023-11-12 11985 struct amdgpu_device *adev = drm_to_adev(connector->dev); f9b4f20c4777bd Stylon Wang 2020-12-04 11986 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; c8133532d2e08c Melissa Wen 2024-09-11 11987 const struct edid *edid; c620e79bb695b8 Rodrigo Siqueira 2022-02-21 11988 bool freesync_capable = false; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 11989 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; b830ebc910f641 Harry Wentland 2017-07-26 11990 8218d7f1f70179 Harry Wentland 2017-10-17 11991 if (!connector->state) { 8218d7f1f70179 Harry Wentland 2017-10-17 11992 DRM_ERROR("%s - Connector has no state", __func__); bb47de73666188 Nicholas Kazlauskas 2018-10-04 11993 goto update; 8218d7f1f70179 Harry Wentland 2017-10-17 11994 } 8218d7f1f70179 Harry Wentland 2017-10-17 11995 9b2fdc33218933 Aurabindo Pillai 2021-08-11 11996 sink = amdgpu_dm_connector->dc_sink ? 9b2fdc33218933 Aurabindo Pillai 2021-08-11 11997 amdgpu_dm_connector->dc_sink : 9b2fdc33218933 Aurabindo Pillai 2021-08-11 11998 amdgpu_dm_connector->dc_em_sink; 9b2fdc33218933 Aurabindo Pillai 2021-08-11 11999 c8133532d2e08c Melissa Wen 2024-09-11 12000 if (!drm_edid || !sink) { 98e6436d3af5fe Anthony Koo 2018-08-21 12001 dm_con_state = to_dm_connector_state(connector->state); 98e6436d3af5fe Anthony Koo 2018-08-21 12002 98e6436d3af5fe Anthony Koo 2018-08-21 12003 amdgpu_dm_connector->min_vfreq = 0; 98e6436d3af5fe Anthony Koo 2018-08-21 12004 amdgpu_dm_connector->max_vfreq = 0; 9b2fdc33218933 Aurabindo Pillai 2021-08-11 12005 connector->display_info.monitor_range.min_vfreq = 0; 9b2fdc33218933 Aurabindo Pillai 2021-08-11 12006 connector->display_info.monitor_range.max_vfreq = 0; 9b2fdc33218933 Aurabindo Pillai 2021-08-11 12007 freesync_capable = false; 98e6436d3af5fe Anthony Koo 2018-08-21 12008 bb47de73666188 Nicholas Kazlauskas 2018-10-04 12009 goto update; 98e6436d3af5fe Anthony Koo 2018-08-21 12010 } 98e6436d3af5fe Anthony Koo 2018-08-21 12011 8218d7f1f70179 Harry Wentland 2017-10-17 12012 dm_con_state = to_dm_connector_state(connector->state); 8218d7f1f70179 Harry Wentland 2017-10-17 12013 e7b07ceef2a650 Harry Wentland 2017-08-10 12014 if (!adev->dm.freesync_module) bb47de73666188 Nicholas Kazlauskas 2018-10-04 12015 goto update; f9b4f20c4777bd Stylon Wang 2020-12-04 12016 c8133532d2e08c Melissa Wen 2024-09-11 12017 edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() c8133532d2e08c Melissa Wen 2024-09-11 12018 a638b837d0e605 Tom Chung 2024-06-14 12019 /* Some eDP panels only have the refresh rate range info in DisplayID */ a638b837d0e605 Tom Chung 2024-06-14 12020 if ((connector->display_info.monitor_range.min_vfreq == 0 || a638b837d0e605 Tom Chung 2024-06-14 12021 connector->display_info.monitor_range.max_vfreq == 0)) a638b837d0e605 Tom Chung 2024-06-14 12022 parse_edid_displayid_vrr(connector, edid); a638b837d0e605 Tom Chung 2024-06-14 12023 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12024 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12025 sink->sink_signal == SIGNAL_TYPE_EDP)) { f9b4f20c4777bd Stylon Wang 2020-12-04 12026 bool edid_check_required = false; f9b4f20c4777bd Stylon Wang 2020-12-04 12027 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12028 if (is_dp_capable_without_timing_msa(adev->dm.dc, 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12029 amdgpu_dm_connector)) { 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12030 if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) { 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12031 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12032 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; 9023ec5d55f399 Tom Chung 2024-06-19 12033 if (amdgpu_dm_connector->max_vfreq - 9023ec5d55f399 Tom Chung 2024-06-19 12034 amdgpu_dm_connector->min_vfreq > 10) 9023ec5d55f399 Tom Chung 2024-06-19 12035 freesync_capable = true; 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12036 } else { 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12037 edid_check_required = edid->version > 1 || 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12038 (edid->version == 1 && 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12039 edid->revision > 1); 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12040 } e7b07ceef2a650 Harry Wentland 2017-08-10 12041 } f9b4f20c4777bd Stylon Wang 2020-12-04 12042 2f14c0c8cae8e9 Mario Limonciello 2024-03-05 12043 if (edid_check_required) { e7b07ceef2a650 Harry Wentland 2017-08-10 12044 for (i = 0; i < 4; i++) { e7b07ceef2a650 Harry Wentland 2017-08-10 12045 e7b07ceef2a650 Harry Wentland 2017-08-10 12046 timing = &edid->detailed_timings[i]; e7b07ceef2a650 Harry Wentland 2017-08-10 12047 data = &timing->data.other_data; e7b07ceef2a650 Harry Wentland 2017-08-10 12048 range = &data->data.range; e7b07ceef2a650 Harry Wentland 2017-08-10 12049 /* e7b07ceef2a650 Harry Wentland 2017-08-10 12050 * Check if monitor has continuous frequency mode e7b07ceef2a650 Harry Wentland 2017-08-10 12051 */ e7b07ceef2a650 Harry Wentland 2017-08-10 12052 if (data->type != EDID_DETAIL_MONITOR_RANGE) e7b07ceef2a650 Harry Wentland 2017-08-10 12053 continue; e7b07ceef2a650 Harry Wentland 2017-08-10 12054 /* e7b07ceef2a650 Harry Wentland 2017-08-10 12055 * Check for flag range limits only. If flag == 1 then e7b07ceef2a650 Harry Wentland 2017-08-10 12056 * no additional timing information provided. e7b07ceef2a650 Harry Wentland 2017-08-10 12057 * Default GTF, GTF Secondary curve and CVT are not e7b07ceef2a650 Harry Wentland 2017-08-10 12058 * supported e7b07ceef2a650 Harry Wentland 2017-08-10 12059 */ e7b07ceef2a650 Harry Wentland 2017-08-10 12060 if (range->flags != 1) e7b07ceef2a650 Harry Wentland 2017-08-10 12061 continue; e7b07ceef2a650 Harry Wentland 2017-08-10 12062 a0ffc3fd67e72b Stylon Wang 2021-01-05 12063 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; a0ffc3fd67e72b Stylon Wang 2021-01-05 12064 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; a0ffc3fd67e72b Stylon Wang 2021-01-05 12065 68e05b932dcba9 Alex Deucher 2024-02-28 12066 if (edid->revision >= 4) { 68e05b932dcba9 Alex Deucher 2024-02-28 12067 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 68e05b932dcba9 Alex Deucher 2024-02-28 12068 connector->display_info.monitor_range.min_vfreq += 255; 68e05b932dcba9 Alex Deucher 2024-02-28 12069 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 68e05b932dcba9 Alex Deucher 2024-02-28 12070 connector->display_info.monitor_range.max_vfreq += 255; 68e05b932dcba9 Alex Deucher 2024-02-28 12071 } 68e05b932dcba9 Alex Deucher 2024-02-28 12072 68e05b932dcba9 Alex Deucher 2024-02-28 12073 amdgpu_dm_connector->min_vfreq = 68e05b932dcba9 Alex Deucher 2024-02-28 12074 connector->display_info.monitor_range.min_vfreq; 68e05b932dcba9 Alex Deucher 2024-02-28 12075 amdgpu_dm_connector->max_vfreq = 68e05b932dcba9 Alex Deucher 2024-02-28 12076 connector->display_info.monitor_range.max_vfreq; 68e05b932dcba9 Alex Deucher 2024-02-28 12077 e7b07ceef2a650 Harry Wentland 2017-08-10 12078 break; e7b07ceef2a650 Harry Wentland 2017-08-10 12079 } e7b07ceef2a650 Harry Wentland 2017-08-10 12080 c84dec2fe8837f Harry Wentland 2017-09-05 12081 if (amdgpu_dm_connector->max_vfreq - c84dec2fe8837f Harry Wentland 2017-09-05 12082 amdgpu_dm_connector->min_vfreq > 10) { 98e6436d3af5fe Anthony Koo 2018-08-21 12083 bb47de73666188 Nicholas Kazlauskas 2018-10-04 12084 freesync_capable = true; e7b07ceef2a650 Harry Wentland 2017-08-10 12085 } e7b07ceef2a650 Harry Wentland 2017-08-10 12086 } ec8e59cb4e0c1a Bhawanpreet Lakha 2023-06-12 12087 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); ec8e59cb4e0c1a Bhawanpreet Lakha 2023-06-12 12088 ec8e59cb4e0c1a Bhawanpreet Lakha 2023-06-12 12089 if (vsdb_info.replay_mode) { ec8e59cb4e0c1a Bhawanpreet Lakha 2023-06-12 12090 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; ec8e59cb4e0c1a Bhawanpreet Lakha 2023-06-12 12091 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; ec8e59cb4e0c1a Bhawanpreet Lakha 2023-06-12 12092 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; ec8e59cb4e0c1a Bhawanpreet Lakha 2023-06-12 12093 } ec8e59cb4e0c1a Bhawanpreet Lakha 2023-06-12 12094 c8133532d2e08c Melissa Wen 2024-09-11 12095 } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 7c7dd77489540d Arnd Bergmann 2021-02-25 12096 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 7c7dd77489540d Arnd Bergmann 2021-02-25 12097 if (i >= 0 && vsdb_info.freesync_supported) { f9b4f20c4777bd Stylon Wang 2020-12-04 12098 timing = &edid->detailed_timings[i]; f9b4f20c4777bd Stylon Wang 2020-12-04 12099 data = &timing->data.other_data; f9b4f20c4777bd Stylon Wang 2020-12-04 12100 f9b4f20c4777bd Stylon Wang 2020-12-04 12101 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12102 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12103 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12104 freesync_capable = true; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12105 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12106 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12107 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12108 } 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12109 } 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12110 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12111 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12112 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12113 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12114 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12115 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12116 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12117 amdgpu_dm_connector->pack_sdp_v1_3 = true; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12118 amdgpu_dm_connector->as_type = as_type; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12119 amdgpu_dm_connector->vsdb_info = vsdb_info; 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12120 5b49da02ddbe1b Sung Joon Kim 2023-01-12 12121 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; f9b4f20c4777bd Stylon Wang 2020-12-04 12122 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; f9b4f20c4777bd Stylon Wang 2020-12-04 12123 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) f9b4f20c4777bd Stylon Wang 2020-12-04 12124 freesync_capable = true; f9b4f20c4777bd Stylon Wang 2020-12-04 12125 f9b4f20c4777bd Stylon Wang 2020-12-04 12126 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; f9b4f20c4777bd Stylon Wang 2020-12-04 12127 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; f9b4f20c4777bd Stylon Wang 2020-12-04 12128 } f9b4f20c4777bd Stylon Wang 2020-12-04 12129 } bb47de73666188 Nicholas Kazlauskas 2018-10-04 12130 bb47de73666188 Nicholas Kazlauskas 2018-10-04 12131 update: bb47de73666188 Nicholas Kazlauskas 2018-10-04 12132 if (dm_con_state) bb47de73666188 Nicholas Kazlauskas 2018-10-04 12133 dm_con_state->freesync_capable = freesync_capable; bb47de73666188 Nicholas Kazlauskas 2018-10-04 12134 bb47de73666188 Nicholas Kazlauskas 2018-10-04 12135 if (connector->vrr_capable_property) bb47de73666188 Nicholas Kazlauskas 2018-10-04 12136 drm_connector_set_vrr_capable_property(connector, bb47de73666188 Nicholas Kazlauskas 2018-10-04 12137 freesync_capable); e7b07ceef2a650 Harry Wentland 2017-08-10 12138 } e7b07ceef2a650 Harry Wentland 2017-08-10 12139
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5942fc4e1c86..4927fdd45073 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3436,7 +3436,7 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); amdgpu_dm_update_freesync_caps(connector, - aconnector->edid); + aconnector->drm_edid); } else { amdgpu_dm_update_freesync_caps(connector, NULL); if (!aconnector->dc_sink) { @@ -3495,18 +3495,19 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); if (sink->dc_edid.length == 0) { - aconnector->edid = NULL; + aconnector->drm_edid = NULL; if (aconnector->dc_link->aux_mode) { drm_dp_cec_unset_edid( &aconnector->dm_dp_aux.aux); } } else { - aconnector->edid = - (struct edid *)sink->dc_edid.raw_edid; + const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; + + aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); + drm_edid_connector_update(connector, aconnector->drm_edid); if (aconnector->dc_link->aux_mode) - drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, - aconnector->edid); + drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, edid); } if (!aconnector->timing_requested) { @@ -3517,17 +3518,18 @@ void amdgpu_dm_update_connector_after_detect( "failed to create aconnector->requested_timing\n"); } - drm_connector_update_edid_property(connector, aconnector->edid); - amdgpu_dm_update_freesync_caps(connector, aconnector->edid); + drm_edid_connector_update(connector, aconnector->drm_edid); + amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid); update_connector_ext_caps(aconnector); } else { drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); amdgpu_dm_update_freesync_caps(connector, NULL); - drm_connector_update_edid_property(connector, NULL); + drm_edid_connector_update(connector, NULL); aconnector->num_modes = 0; dc_sink_release(aconnector->dc_sink); aconnector->dc_sink = NULL; - aconnector->edid = NULL; + drm_edid_free(aconnector->drm_edid); + aconnector->drm_edid = NULL; kfree(aconnector->timing_requested); aconnector->timing_requested = NULL; /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ @@ -7041,32 +7043,24 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dc_link *dc_link = aconnector->dc_link; struct dc_sink *dc_em_sink = aconnector->dc_em_sink; - struct edid *edid; - struct i2c_adapter *ddc; - - if (dc_link && dc_link->aux_mode) - ddc = &aconnector->dm_dp_aux.aux.ddc; - else - ddc = &aconnector->i2c->base; + const struct drm_edid *drm_edid; - /* - * Note: drm_get_edid gets edid in the following order: - * 1) override EDID if set via edid_override debugfs, - * 2) firmware EDID if set via edid_firmware module parameter - * 3) regular DDC read. - */ - edid = drm_get_edid(connector, ddc); - if (!edid) { + drm_edid = drm_edid_read(connector); + drm_edid_connector_update(connector, drm_edid); + if (!drm_edid) { DRM_ERROR("No EDID found on connector: %s.\n", connector->name); return; } - aconnector->edid = edid; - + aconnector->drm_edid = drm_edid; /* Update emulated (virtual) sink's EDID */ if (dc_em_sink && dc_link) { + // FIXME: Get rid of drm_edid_raw() + const struct edid *edid = drm_edid_raw(drm_edid); + memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); - memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); + memmove(dc_em_sink->dc_edid.raw_edid, edid, + (edid->extensions + 1) * EDID_LENGTH); dm_helpers_parse_edid_caps( dc_link, &dc_em_sink->dc_edid, @@ -7096,36 +7090,26 @@ static int get_modes(struct drm_connector *connector) static void create_eml_sink(struct amdgpu_dm_connector *aconnector) { struct drm_connector *connector = &aconnector->base; - struct dc_link *dc_link = aconnector->dc_link; struct dc_sink_init_data init_params = { .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_VIRTUAL }; - struct edid *edid; - struct i2c_adapter *ddc; - - if (dc_link->aux_mode) - ddc = &aconnector->dm_dp_aux.aux.ddc; - else - ddc = &aconnector->i2c->base; + const struct drm_edid *drm_edid; + const struct edid *edid; - /* - * Note: drm_get_edid gets edid in the following order: - * 1) override EDID if set via edid_override debugfs, - * 2) firmware EDID if set via edid_firmware module parameter - * 3) regular DDC read. - */ - edid = drm_get_edid(connector, ddc); - if (!edid) { + drm_edid = drm_edid_read(connector); + drm_edid_connector_update(connector, drm_edid); + if (!drm_edid) { DRM_ERROR("No EDID found on connector: %s.\n", connector->name); return; } - if (drm_detect_hdmi_monitor(edid)) + if (connector->display_info.is_hdmi) init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; - aconnector->edid = edid; + aconnector->drm_edid = drm_edid; + edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() aconnector->dc_em_sink = dc_link_add_remote_sink( aconnector->dc_link, (uint8_t *)edid, @@ -7809,16 +7793,16 @@ static void amdgpu_set_panel_orientation(struct drm_connector *connector) } static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, - struct edid *edid) + const struct drm_edid *drm_edid) { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); - if (edid) { + if (drm_edid) { /* empty probed_modes */ INIT_LIST_HEAD(&connector->probed_modes); amdgpu_dm_connector->num_modes = - drm_add_edid_modes(connector, edid); + drm_edid_connector_add_modes(connector); /* sorting the probed modes before calling function * amdgpu_dm_get_native_mode() since EDID can have @@ -7832,10 +7816,10 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, amdgpu_dm_get_native_mode(connector); /* Freesync capabilities are reset by calling - * drm_add_edid_modes() and need to be + * drm_edid_connector_add_modes() and need to be * restored here. */ - amdgpu_dm_update_freesync_caps(connector, edid); + amdgpu_dm_update_freesync_caps(connector, drm_edid); } else { amdgpu_dm_connector->num_modes = 0; } @@ -7931,12 +7915,12 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) } static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, - struct edid *edid) + const struct drm_edid *drm_edid) { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); - if (!(amdgpu_freesync_vid_mode && edid)) + if (!(amdgpu_freesync_vid_mode && drm_edid)) return; if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) @@ -7949,24 +7933,24 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); struct drm_encoder *encoder; - struct edid *edid = amdgpu_dm_connector->edid; + const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid; struct dc_link_settings *verified_link_cap = &amdgpu_dm_connector->dc_link->verified_link_cap; const struct dc *dc = amdgpu_dm_connector->dc_link->dc; encoder = amdgpu_dm_connector_to_encoder(connector); - if (!drm_edid_is_valid(edid)) { + if (!drm_edid) { amdgpu_dm_connector->num_modes = drm_add_modes_noedid(connector, 640, 480); if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) amdgpu_dm_connector->num_modes += drm_add_modes_noedid(connector, 1920, 1080); } else { - amdgpu_dm_connector_ddc_get_modes(connector, edid); + amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); if (encoder) amdgpu_dm_connector_add_common_modes(encoder, connector); - amdgpu_dm_connector_add_freesync_modes(connector, edid); + amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); } amdgpu_dm_fbc_init(connector); @@ -11905,7 +11889,7 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, } static void parse_edid_displayid_vrr(struct drm_connector *connector, - struct edid *edid) + const struct edid *edid) { u8 *edid_ext = NULL; int i; @@ -11948,7 +11932,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, } static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, - struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) + const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) { u8 *edid_ext = NULL; int i; @@ -11983,7 +11967,8 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, } static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, - struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) + const struct edid *edid, + struct amdgpu_hdmi_vsdb_info *vsdb_info) { u8 *edid_ext = NULL; int i; @@ -12025,19 +12010,19 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, * FreeSync parameters. */ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, - struct edid *edid) + const struct drm_edid *drm_edid) { int i = 0; - struct detailed_timing *timing; - struct detailed_non_pixel *data; - struct detailed_data_monitor_range *range; + const struct detailed_timing *timing; + const struct detailed_non_pixel *data; + const struct detailed_data_monitor_range *range; struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); struct dm_connector_state *dm_con_state = NULL; struct dc_sink *sink; - struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; + const struct edid *edid; bool freesync_capable = false; enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; @@ -12050,7 +12035,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->dc_sink : amdgpu_dm_connector->dc_em_sink; - if (!edid || !sink) { + if (!drm_edid || !sink) { dm_con_state = to_dm_connector_state(connector->state); amdgpu_dm_connector->min_vfreq = 0; @@ -12067,6 +12052,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (!adev->dm.freesync_module) goto update; + edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() + /* Some eDP panels only have the refresh rate range info in DisplayID */ if ((connector->display_info.monitor_range.min_vfreq == 0 || connector->display_info.monitor_range.max_vfreq == 0)) @@ -12143,7 +12130,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; } - } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { + } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); if (i >= 0 && vsdb_info.freesync_supported) { timing = &edid->detailed_timings[i]; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 2d7755e2b6c3..c231d3058db8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -673,7 +673,7 @@ struct amdgpu_dm_connector { /* we need to mind the EDID between detect and get modes due to analog/digital/tvencoder */ - struct edid *edid; + const struct drm_edid *drm_edid; /* shared with amdgpu */ struct amdgpu_hpd hpd; @@ -951,7 +951,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, - struct edid *edid); + const struct drm_edid *drm_edid); void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index b490ae67b6be..be72f14f5429 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -897,7 +897,8 @@ enum dc_edid_status dm_helpers_read_local_edid( struct i2c_adapter *ddc; int retry = 3; enum dc_edid_status edid_status; - struct edid *edid; + const struct drm_edid *drm_edid; + const struct edid *edid; if (link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; @@ -909,25 +910,27 @@ enum dc_edid_status dm_helpers_read_local_edid( */ do { - edid = drm_get_edid(&aconnector->base, ddc); + drm_edid = drm_edid_read_ddc(connector, ddc); + drm_edid_connector_update(connector, drm_edid); /* DP Compliance Test 4.2.2.6 */ if (link->aux_mode && connector->edid_corrupt) drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); - if (!edid && connector->edid_corrupt) { + if (!drm_edid && connector->edid_corrupt) { connector->edid_corrupt = false; return EDID_BAD_CHECKSUM; } - if (!edid) + if (!drm_edid) return EDID_NO_RESPONSE; + edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); /* We don't need the original edid anymore */ - kfree(edid); + drm_edid_free(drm_edid); edid_status = dm_helpers_parse_edid_caps( link, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 2e9f6da1acdc..90a80e799d8b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -129,7 +129,7 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) dc_sink_release(aconnector->dc_sink); } - kfree(aconnector->edid); + drm_edid_free(aconnector->drm_edid); drm_connector_cleanup(connector); drm_dp_mst_put_port_malloc(aconnector->mst_output_port); @@ -182,7 +182,7 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) dc_sink_release(dc_sink); aconnector->dc_sink = NULL; - aconnector->edid = NULL; + aconnector->drm_edid = NULL; aconnector->dsc_aux = NULL; port->passthrough_aux = NULL; } @@ -302,16 +302,18 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!aconnector) return drm_add_edid_modes(connector, NULL); - if (!aconnector->edid) { - struct edid *edid; + if (!aconnector->drm_edid) { + const struct drm_edid *drm_edid; - edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); + drm_edid = drm_dp_mst_edid_read(connector, + &aconnector->mst_root->mst_mgr, + aconnector->mst_output_port); - if (!edid) { + if (!drm_edid) { amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID, false); - drm_connector_update_edid_property( + drm_edid_connector_update( &aconnector->base, NULL); @@ -345,7 +347,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) return ret; } - aconnector->edid = edid; + aconnector->drm_edid = drm_edid; amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID, true); } @@ -360,10 +362,13 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) struct dc_sink_init_data init_params = { .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; + const struct edid *edid; + + edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw() dc_sink = dc_link_add_remote_sink( aconnector->dc_link, - (uint8_t *)aconnector->edid, - (aconnector->edid->extensions + 1) * EDID_LENGTH, + (uint8_t *)edid, + (edid->extensions + 1) * EDID_LENGTH, &init_params); if (!dc_sink) { @@ -405,7 +410,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( - connector, aconnector->edid); + connector, aconnector->drm_edid); #if defined(CONFIG_DRM_AMD_DC_FP) if (!validate_dsc_caps_on_connector(aconnector)) @@ -419,10 +424,9 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) } } - drm_connector_update_edid_property( - &aconnector->base, aconnector->edid); + drm_edid_connector_update(&aconnector->base, aconnector->drm_edid); - ret = drm_add_edid_modes(connector, aconnector->edid); + ret = drm_edid_connector_add_modes(connector); return ret; } @@ -500,7 +504,7 @@ dm_dp_mst_detect(struct drm_connector *connector, dc_sink_release(aconnector->dc_sink); aconnector->dc_sink = NULL; - aconnector->edid = NULL; + aconnector->drm_edid = NULL; aconnector->dsc_aux = NULL; port->passthrough_aux = NULL;