| Message ID | 20240916082307.29393-3-johan+linaro@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 27727cb6604e0998d03d9ec063b517b239d2bb0f |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: fix missing PCIe PHY clocks | expand |
On 24-09-16 10:23:06, Johan Hovold wrote: > Add the missing clkref enable and pipediv2 clocks to the PCIe4 and > PCIe6a PHYs. > > Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") > Cc: stable@vger.kernel.org # 6.9 > Cc: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 ++++++++++------ > 1 file changed, 10 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 0cf4f3c12428..53e7d1e603cb 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -2980,14 +2980,16 @@ pcie6a_phy: phy@1bfc000 { > > clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, > <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, > - <&rpmhcc RPMH_CXO_CLK>, > + <&tcsr TCSR_PCIE_4L_CLKREF_EN>, > <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, > - <&gcc GCC_PCIE_6A_PIPE_CLK>; > + <&gcc GCC_PCIE_6A_PIPE_CLK>, > + <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; > clock-names = "aux", > "cfg_ahb", > "ref", > "rchng", > - "pipe"; > + "pipe", > + "pipediv2"; > > resets = <&gcc GCC_PCIE_6A_PHY_BCR>, > <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; > @@ -3232,14 +3234,16 @@ pcie4_phy: phy@1c0e000 { > > clocks = <&gcc GCC_PCIE_4_AUX_CLK>, > <&gcc GCC_PCIE_4_CFG_AHB_CLK>, > - <&rpmhcc RPMH_CXO_CLK>, > + <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, > <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, > - <&gcc GCC_PCIE_4_PIPE_CLK>; > + <&gcc GCC_PCIE_4_PIPE_CLK>, > + <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; > clock-names = "aux", > "cfg_ahb", > "ref", > "rchng", > - "pipe"; > + "pipe", > + "pipediv2"; > > resets = <&gcc GCC_PCIE_4_PHY_BCR>; > reset-names = "phy"; > -- > 2.44.2 >
On 16.09.2024 10:23 AM, Johan Hovold wrote: > Add the missing clkref enable and pipediv2 clocks to the PCIe4 and > PCIe6a PHYs. > > Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") > Cc: stable@vger.kernel.org # 6.9 > Cc: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > --- I reckon you split it like you day so that it's easier to backport.. Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Konrad
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 0cf4f3c12428..53e7d1e603cb 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2980,14 +2980,16 @@ pcie6a_phy: phy@1bfc000 { clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_PCIE_4L_CLKREF_EN>, <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_6A_PIPE_CLK>; + <&gcc GCC_PCIE_6A_PIPE_CLK>, + <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + "pipe", + "pipediv2"; resets = <&gcc GCC_PCIE_6A_PHY_BCR>, <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; @@ -3232,14 +3234,16 @@ pcie4_phy: phy@1c0e000 { clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_4_PIPE_CLK>; + <&gcc GCC_PCIE_4_PIPE_CLK>, + <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + "pipe", + "pipediv2"; resets = <&gcc GCC_PCIE_4_PHY_BCR>; reset-names = "phy";
Add the missing clkref enable and pipediv2 clocks to the PCIe4 and PCIe6a PHYs. Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Cc: stable@vger.kernel.org # 6.9 Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-)