| Message ID | 20240916200255.2566209-1-diogo.pais@ttcontrol.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8: Fix lvds0 device tree | expand |
On 16/09/2024 22:02, Diogo Silva wrote: > From: Diogo Silva <diogompaissilva@gmail.com> > > Some clock output names on lvds0 device tree were duplicated from mipi1, > which caused an -EEXIST when registering these clocks during probe. > Also fixed the device naming to be consistent with lvds1. > > Fixes: 0fba24b3b956 ("arm64: dts: imx8: add basic lvds0 and lvds1 subsystem") > subsystem") Broken tags. They do not line-brake, BTW. > Signed-off-by: Diogo Silva <diogompaissilva@gmail.com> > --- > .../boot/dts/freescale/imx8-ss-lvds0.dtsi | 22 +++++++++---------- > arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 4 ++-- > .../boot/dts/freescale/imx8qm-ss-lvds.dtsi | 20 ++++++++--------- > 3 files changed, 23 insertions(+), 23 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi > index d00036204a8c..a4d94467039f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi > @@ -10,34 +10,34 @@ lvds0_subsys: bus@56240000 { > #size-cells = <1>; > ranges = <0x56240000 0x0 0x56240000 0x10000>; > > - qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 { > + lvds0_lis_lpcg: clock-controller@56243000 { > compatible = "fsl,imx8qxp-lpcg"; > reg = <0x56243000 0x4>; > #clock-cells = <1>; > - clock-output-names = "mipi1_lis_lpcg_ipg_clk"; > + clock-output-names = "lvds0_lis_lpcg_ipg_clk"; > power-domains = <&pd IMX_SC_R_MIPI_1>; > }; > > - qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c { > + lvds0_pwm_lpcg: clock-controller@5624300c { > compatible = "fsl,imx8qxp-lpcg"; > reg = <0x5624300c 0x4>; > #clock-cells = <1>; > - clock-output-names = "mipi1_pwm_lpcg_clk", > - "mipi1_pwm_lpcg_ipg_clk", > - "mipi1_pwm_lpcg_32k_clk"; > + clock-output-names = "lvds0_pwm_lpcg_clk", > + "lvds0_pwm_lpcg_ipg_clk", > + "lvds0_pwm_lpcg_32k_clk"; > power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; > }; > > - qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 { > + lvds0_i2c0_lpcg: clock-controller@56243010 { > compatible = "fsl,imx8qxp-lpcg"; > reg = <0x56243010 0x4>; > #clock-cells = <1>; > - clock-output-names = "mipi1_i2c0_lpcg_clk", > - "mipi1_i2c0_lpcg_ipg_clk"; > + clock-output-names = "lvds0_i2c0_lpcg_clk", > + "lvds0_i2c0_lpcg_ipg_clk"; > power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; > }; > > - qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 { > + pwm_lvds0: pwm@56244000 { > compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; > reg = <0x56244000 0x1000>; > clock-names = "ipg", "per"; > @@ -48,7 +48,7 @@ qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 { > status = "disabled"; > }; > > - qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 { > + i2c0_lvds0: i2c@56246000 { > compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > reg = <0x56246000 0x1000>; > #address-cells = <1>; > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts > index 62203eed6a6c..f7b9b319a58a 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts > +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts > @@ -96,7 +96,7 @@ vdevbuffer: memory@90400000 { > > lvds_backlight0: backlight-lvds0 { > compatible = "pwm-backlight"; > - pwms = <&qm_pwm_lvds0 0 100000 0>; > + pwms = <&pwm_lvds0 0 100000 0>; > brightness-levels = <0 100>; > num-interpolated-steps = <100>; > default-brightness-level = <80>; > @@ -541,7 +541,7 @@ &fec2 { > status = "okay"; > }; > > -&qm_pwm_lvds0 { > +&pwm_lvds0 { Why this cannot stay qm_pwm_lvds0? Are you sure nodes now have correct order? Best regards, Krzysztof
Hey, Sorry for the broken tag, will fix on a resend. As for the naming, if there is any reason for them to be named qm_* it's totally fine, I'll revert it and only touch the clock names. I changed them because comparing with lvds1, those ones do not contain the qm_ prefix and I don't see how this dtsi relates specifically to the imx8qm, since it is a imx8-ss... and not imx8qm-ss... I didn't quite get the question about the nodes. Could you elaborate? Thanks Best regards, Diogo On Mon, 16 Sept 2024 at 22:23, Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 16/09/2024 22:02, Diogo Silva wrote: > > From: Diogo Silva <diogompaissilva@gmail.com> > > > > Some clock output names on lvds0 device tree were duplicated from mipi1, > > which caused an -EEXIST when registering these clocks during probe. > > Also fixed the device naming to be consistent with lvds1. > > > > Fixes: 0fba24b3b956 ("arm64: dts: imx8: add basic lvds0 and lvds1 subsystem") > > subsystem") > > Broken tags. They do not line-brake, BTW. > > > Signed-off-by: Diogo Silva <diogompaissilva@gmail.com> > > --- > > .../boot/dts/freescale/imx8-ss-lvds0.dtsi | 22 +++++++++---------- > > arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 4 ++-- > > .../boot/dts/freescale/imx8qm-ss-lvds.dtsi | 20 ++++++++--------- > > 3 files changed, 23 insertions(+), 23 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi > > index d00036204a8c..a4d94467039f 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi > > @@ -10,34 +10,34 @@ lvds0_subsys: bus@56240000 { > > #size-cells = <1>; > > ranges = <0x56240000 0x0 0x56240000 0x10000>; > > > > - qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 { > > + lvds0_lis_lpcg: clock-controller@56243000 { > > compatible = "fsl,imx8qxp-lpcg"; > > reg = <0x56243000 0x4>; > > #clock-cells = <1>; > > - clock-output-names = "mipi1_lis_lpcg_ipg_clk"; > > + clock-output-names = "lvds0_lis_lpcg_ipg_clk"; > > power-domains = <&pd IMX_SC_R_MIPI_1>; > > }; > > > > - qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c { > > + lvds0_pwm_lpcg: clock-controller@5624300c { > > compatible = "fsl,imx8qxp-lpcg"; > > reg = <0x5624300c 0x4>; > > #clock-cells = <1>; > > - clock-output-names = "mipi1_pwm_lpcg_clk", > > - "mipi1_pwm_lpcg_ipg_clk", > > - "mipi1_pwm_lpcg_32k_clk"; > > + clock-output-names = "lvds0_pwm_lpcg_clk", > > + "lvds0_pwm_lpcg_ipg_clk", > > + "lvds0_pwm_lpcg_32k_clk"; > > power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; > > }; > > > > - qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 { > > + lvds0_i2c0_lpcg: clock-controller@56243010 { > > compatible = "fsl,imx8qxp-lpcg"; > > reg = <0x56243010 0x4>; > > #clock-cells = <1>; > > - clock-output-names = "mipi1_i2c0_lpcg_clk", > > - "mipi1_i2c0_lpcg_ipg_clk"; > > + clock-output-names = "lvds0_i2c0_lpcg_clk", > > + "lvds0_i2c0_lpcg_ipg_clk"; > > power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; > > }; > > > > - qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 { > > + pwm_lvds0: pwm@56244000 { > > compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; > > reg = <0x56244000 0x1000>; > > clock-names = "ipg", "per"; > > @@ -48,7 +48,7 @@ qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 { > > status = "disabled"; > > }; > > > > - qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 { > > + i2c0_lvds0: i2c@56246000 { > > compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > > reg = <0x56246000 0x1000>; > > #address-cells = <1>; > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts > > index 62203eed6a6c..f7b9b319a58a 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts > > +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts > > @@ -96,7 +96,7 @@ vdevbuffer: memory@90400000 { > > > > lvds_backlight0: backlight-lvds0 { > > compatible = "pwm-backlight"; > > - pwms = <&qm_pwm_lvds0 0 100000 0>; > > + pwms = <&pwm_lvds0 0 100000 0>; > > brightness-levels = <0 100>; > > num-interpolated-steps = <100>; > > default-brightness-level = <80>; > > @@ -541,7 +541,7 @@ &fec2 { > > status = "okay"; > > }; > > > > -&qm_pwm_lvds0 { > > +&pwm_lvds0 { > > Why this cannot stay qm_pwm_lvds0? Are you sure nodes now have correct > order? > > > > Best regards, > Krzysztof >
On 16/09/2024 22:47, Diogo Silva wrote: > Hey, > > Sorry for the broken tag, will fix on a resend. > > As for the naming, if there is any reason for them to be named qm_* it's > totally fine, I'll revert it and only touch the clock names. I changed them It's just unnecessary. > because comparing with lvds1, those ones do not contain the qm_ prefix and > I don't see how this dtsi relates specifically to the imx8qm, since it is a > imx8-ss... and not imx8qm-ss... > I didn't quite get the question about the nodes. Could you elaborate? Thanks > Usually they have alphabetical order and your change does not look like keeping it. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi index d00036204a8c..a4d94467039f 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi @@ -10,34 +10,34 @@ lvds0_subsys: bus@56240000 { #size-cells = <1>; ranges = <0x56240000 0x0 0x56240000 0x10000>; - qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 { + lvds0_lis_lpcg: clock-controller@56243000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x56243000 0x4>; #clock-cells = <1>; - clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + clock-output-names = "lvds0_lis_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_MIPI_1>; }; - qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c { + lvds0_pwm_lpcg: clock-controller@5624300c { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5624300c 0x4>; #clock-cells = <1>; - clock-output-names = "mipi1_pwm_lpcg_clk", - "mipi1_pwm_lpcg_ipg_clk", - "mipi1_pwm_lpcg_32k_clk"; + clock-output-names = "lvds0_pwm_lpcg_clk", + "lvds0_pwm_lpcg_ipg_clk", + "lvds0_pwm_lpcg_32k_clk"; power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; }; - qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 { + lvds0_i2c0_lpcg: clock-controller@56243010 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x56243010 0x4>; #clock-cells = <1>; - clock-output-names = "mipi1_i2c0_lpcg_clk", - "mipi1_i2c0_lpcg_ipg_clk"; + clock-output-names = "lvds0_i2c0_lpcg_clk", + "lvds0_i2c0_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; }; - qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 { + pwm_lvds0: pwm@56244000 { compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; reg = <0x56244000 0x1000>; clock-names = "ipg", "per"; @@ -48,7 +48,7 @@ qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 { status = "disabled"; }; - qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 { + i2c0_lvds0: i2c@56246000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x56246000 0x1000>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 62203eed6a6c..f7b9b319a58a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -96,7 +96,7 @@ vdevbuffer: memory@90400000 { lvds_backlight0: backlight-lvds0 { compatible = "pwm-backlight"; - pwms = <&qm_pwm_lvds0 0 100000 0>; + pwms = <&pwm_lvds0 0 100000 0>; brightness-levels = <0 100>; num-interpolated-steps = <100>; default-brightness-level = <80>; @@ -541,7 +541,7 @@ &fec2 { status = "okay"; }; -&qm_pwm_lvds0 { +&pwm_lvds0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_lvds0>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi index 0514d8b2af75..46fa97d5ba5c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi @@ -4,31 +4,31 @@ * Copyright 2024 NXP */ -&qm_lvds0_lis_lpcg { +&lvds0_lis_lpcg { clocks = <&lvds_ipg_clk>; clock-indices = <IMX_LPCG_CLK_4>; }; -&qm_lvds0_pwm_lpcg { +&lvds0_pwm_lpcg { clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, <&lvds_ipg_clk>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; }; -&qm_lvds0_i2c0_lpcg { +&lvds0_i2c0_lpcg { clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, <&lvds_ipg_clk>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; }; -&qm_pwm_lvds0 { - clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4>, - <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0>; +&pwm_lvds0 { + clocks = <&lvds0_pwm_lpcg IMX_LPCG_CLK_4>, + <&lvds0_pwm_lpcg IMX_LPCG_CLK_0>; }; -&qm_i2c0_lvds0 { - clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0>, - <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4>; +&i2c0_lvds0 { + clocks = <&lvds0_i2c0_lpcg IMX_LPCG_CLK_0>, + <&lvds0_i2c0_lpcg IMX_LPCG_CLK_4>; }; &lvds0_subsys { @@ -41,7 +41,7 @@ irqsteer_lvds0: interrupt-controller@56240000 { interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <1>; - clocks = <&qm_lvds0_lis_lpcg IMX_LPCG_CLK_4>; + clocks = <&lvds0_lis_lpcg IMX_LPCG_CLK_4>; clock-names = "ipg"; power-domains = <&pd IMX_SC_R_LVDS_0>;