| Message ID | 20240916082307.29393-4-johan+linaro@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 0b80b3c0f6d20f1bc1f7fea6176a8df15619e884 |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: fix missing PCIe PHY clocks | expand |
On 16.09.2024 10:23 AM, Johan Hovold wrote: > Add the missing clkref enable and pipediv2 clocks to the PCIe5 PHY. > > Fixes: 62ab23e15508 ("arm64: dts: qcom: x1e80100: add PCIe5 nodes") > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > --- Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Konrad
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 53e7d1e603cb..d1bb14a375c3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3104,14 +3104,16 @@ pcie5_phy: phy@1c06000 { clocks = <&gcc GCC_PCIE_5_AUX_CLK>, <&gcc GCC_PCIE_5_CFG_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_5_PIPE_CLK>; + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + "pipe", + "pipediv2"; resets = <&gcc GCC_PCIE_5_PHY_BCR>; reset-names = "phy";
Add the missing clkref enable and pipediv2 clocks to the PCIe5 PHY. Fixes: 62ab23e15508 ("arm64: dts: qcom: x1e80100: add PCIe5 nodes") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)