| Message ID | 20240917174200.2563528-2-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Implement Wa_14021768792 to bypass m_n ratio limit | expand |
On Tue, 17 Sep 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: > LINK_N register has bits 31:24 for extended link N value used for > HDMI2.1 and for an alternate mode of operation of DP TG DDA > (Bspec:50488). > > Add support for these extra bits. > > v2: Drop extra link_n_ext member. (Jani) > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++----- > drivers/gpu/drm/i915/display/intel_display.h | 2 +- > .../gpu/drm/i915/display/intel_pch_display.c | 4 ++-- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 4 files changed, 21 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 426074afef43..4b1bb1f43adb 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2633,9 +2633,12 @@ void intel_zero_m_n(struct intel_link_m_n *m_n) > > void intel_set_m_n(struct drm_i915_private *i915, > const struct intel_link_m_n *m_n, > + u8 link_n_ext, > i915_reg_t data_m_reg, i915_reg_t data_n_reg, > i915_reg_t link_m_reg, i915_reg_t link_n_reg) > { > + u8 link_n = m_n->link_n; You also don't need the parameter. You don't need to pass it around. Please read my previous review. BR, Jani. > + > intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); > intel_de_write(i915, data_n_reg, m_n->data_n); > intel_de_write(i915, link_m_reg, m_n->link_m); > @@ -2643,7 +2646,11 @@ void intel_set_m_n(struct drm_i915_private *i915, > * On BDW+ writing LINK_N arms the double buffered update > * of all the M/N registers, so it must be written last. > */ > - intel_de_write(i915, link_n_reg, m_n->link_n); > + > + if (DISPLAY_VER(i915) >= 14 && link_n_ext) > + link_n |= PIPE_LINK_N1_EXTENDED(link_n_ext); > + > + intel_de_write(i915, link_n_reg, link_n); > } > > bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, > @@ -2663,13 +2670,13 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, > enum pipe pipe = crtc->pipe; > > if (DISPLAY_VER(dev_priv) >= 5) > - intel_set_m_n(dev_priv, m_n, > + intel_set_m_n(dev_priv, m_n, 0, > PIPE_DATA_M1(dev_priv, transcoder), > PIPE_DATA_N1(dev_priv, transcoder), > PIPE_LINK_M1(dev_priv, transcoder), > PIPE_LINK_N1(dev_priv, transcoder)); > else > - intel_set_m_n(dev_priv, m_n, > + intel_set_m_n(dev_priv, m_n, 0, > PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), > PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); > } > @@ -2683,7 +2690,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, > if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) > return; > > - intel_set_m_n(dev_priv, m_n, > + intel_set_m_n(dev_priv, m_n, 0, > PIPE_DATA_M2(dev_priv, transcoder), > PIPE_DATA_N2(dev_priv, transcoder), > PIPE_LINK_M2(dev_priv, transcoder), > @@ -3351,7 +3358,11 @@ void intel_get_m_n(struct drm_i915_private *i915, > i915_reg_t link_m_reg, i915_reg_t link_n_reg) > { > m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; > - m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; > + m_n->link_n = intel_de_read(i915, link_n_reg); > + > + if (DISPLAY_VER(i915) < 14) > + m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK; > + > m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; > m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; > m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h > index 4bdb48084cab..3b12d7f7c6c3 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.h > +++ b/drivers/gpu/drm/i915/display/intel_display.h > @@ -473,7 +473,7 @@ bool intel_fuzzy_clock_check(int clock1, int clock2); > > void intel_zero_m_n(struct intel_link_m_n *m_n); > void intel_set_m_n(struct drm_i915_private *i915, > - const struct intel_link_m_n *m_n, > + const struct intel_link_m_n *m_n, u8 link_n_ext, > i915_reg_t data_m_reg, i915_reg_t data_n_reg, > i915_reg_t link_m_reg, i915_reg_t link_n_reg); > void intel_get_m_n(struct drm_i915_private *i915, > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c > index f13ab680c2cf..74bc4de6d123 100644 > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c > @@ -178,7 +178,7 @@ static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > > - intel_set_m_n(dev_priv, m_n, > + intel_set_m_n(dev_priv, m_n, 0, > PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), > PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); > } > @@ -189,7 +189,7 @@ static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > > - intel_set_m_n(dev_priv, m_n, > + intel_set_m_n(dev_priv, m_n, 0, > PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), > PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7396fc630e29..a770b5dbf5e4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2158,6 +2158,8 @@ > > #define _PIPEA_LINK_N1 0x60044 > #define _PIPEB_LINK_N1 0x61044 > +#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24) > +#define PIPE_LINK_N1_EXTENDED(val) REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val)) > #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) > > #define _PIPEA_LINK_M2 0x60048
On 9/17/2024 11:16 PM, Jani Nikula wrote: > On Tue, 17 Sep 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: >> LINK_N register has bits 31:24 for extended link N value used for >> HDMI2.1 and for an alternate mode of operation of DP TG DDA >> (Bspec:50488). >> >> Add support for these extra bits. >> >> v2: Drop extra link_n_ext member. (Jani) >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++----- >> drivers/gpu/drm/i915/display/intel_display.h | 2 +- >> .../gpu/drm/i915/display/intel_pch_display.c | 4 ++-- >> drivers/gpu/drm/i915/i915_reg.h | 2 ++ >> 4 files changed, 21 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >> index 426074afef43..4b1bb1f43adb 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display.c >> +++ b/drivers/gpu/drm/i915/display/intel_display.c >> @@ -2633,9 +2633,12 @@ void intel_zero_m_n(struct intel_link_m_n *m_n) >> >> void intel_set_m_n(struct drm_i915_private *i915, >> const struct intel_link_m_n *m_n, >> + u8 link_n_ext, >> i915_reg_t data_m_reg, i915_reg_t data_n_reg, >> i915_reg_t link_m_reg, i915_reg_t link_n_reg) >> { >> + u8 link_n = m_n->link_n; > You also don't need the parameter. You don't need to pass it > around. Please read my previous review. Thank you for your feedback. I was trying to avoid mixing link_n with link_n_ext bits, which as I understand gets filled with different kinds of things. If we want to have link_n along with ext bits, then perhaps we need to mask these whenever we want to retrieve link_n. So I will: ->mask the extended bits in this patch, as suggested. ->have link_n filled with extended bits during compute_config if required, in intel_link_compute_m_n() ->change the places where m_n->link_n is used (e.g in intel_dotclock_calculate() ) to mask the extended bits, before use. Please let me know if this approach seems alright or if there is another way you would prefer. Thanks & Regards, Ankit > > BR, > Jani. > >> + >> intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); >> intel_de_write(i915, data_n_reg, m_n->data_n); >> intel_de_write(i915, link_m_reg, m_n->link_m); >> @@ -2643,7 +2646,11 @@ void intel_set_m_n(struct drm_i915_private *i915, >> * On BDW+ writing LINK_N arms the double buffered update >> * of all the M/N registers, so it must be written last. >> */ >> - intel_de_write(i915, link_n_reg, m_n->link_n); >> + >> + if (DISPLAY_VER(i915) >= 14 && link_n_ext) >> + link_n |= PIPE_LINK_N1_EXTENDED(link_n_ext); >> + >> + intel_de_write(i915, link_n_reg, link_n); >> } >> >> bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, >> @@ -2663,13 +2670,13 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, >> enum pipe pipe = crtc->pipe; >> >> if (DISPLAY_VER(dev_priv) >= 5) >> - intel_set_m_n(dev_priv, m_n, >> + intel_set_m_n(dev_priv, m_n, 0, >> PIPE_DATA_M1(dev_priv, transcoder), >> PIPE_DATA_N1(dev_priv, transcoder), >> PIPE_LINK_M1(dev_priv, transcoder), >> PIPE_LINK_N1(dev_priv, transcoder)); >> else >> - intel_set_m_n(dev_priv, m_n, >> + intel_set_m_n(dev_priv, m_n, 0, >> PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), >> PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); >> } >> @@ -2683,7 +2690,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, >> if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) >> return; >> >> - intel_set_m_n(dev_priv, m_n, >> + intel_set_m_n(dev_priv, m_n, 0, >> PIPE_DATA_M2(dev_priv, transcoder), >> PIPE_DATA_N2(dev_priv, transcoder), >> PIPE_LINK_M2(dev_priv, transcoder), >> @@ -3351,7 +3358,11 @@ void intel_get_m_n(struct drm_i915_private *i915, >> i915_reg_t link_m_reg, i915_reg_t link_n_reg) >> { >> m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; >> - m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; >> + m_n->link_n = intel_de_read(i915, link_n_reg); >> + >> + if (DISPLAY_VER(i915) < 14) >> + m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK; >> + >> m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; >> m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; >> m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; >> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h >> index 4bdb48084cab..3b12d7f7c6c3 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display.h >> +++ b/drivers/gpu/drm/i915/display/intel_display.h >> @@ -473,7 +473,7 @@ bool intel_fuzzy_clock_check(int clock1, int clock2); >> >> void intel_zero_m_n(struct intel_link_m_n *m_n); >> void intel_set_m_n(struct drm_i915_private *i915, >> - const struct intel_link_m_n *m_n, >> + const struct intel_link_m_n *m_n, u8 link_n_ext, >> i915_reg_t data_m_reg, i915_reg_t data_n_reg, >> i915_reg_t link_m_reg, i915_reg_t link_n_reg); >> void intel_get_m_n(struct drm_i915_private *i915, >> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c >> index f13ab680c2cf..74bc4de6d123 100644 >> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c >> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c >> @@ -178,7 +178,7 @@ static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> enum pipe pipe = crtc->pipe; >> >> - intel_set_m_n(dev_priv, m_n, >> + intel_set_m_n(dev_priv, m_n, 0, >> PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), >> PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); >> } >> @@ -189,7 +189,7 @@ static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> enum pipe pipe = crtc->pipe; >> >> - intel_set_m_n(dev_priv, m_n, >> + intel_set_m_n(dev_priv, m_n, 0, >> PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), >> PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); >> } >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 7396fc630e29..a770b5dbf5e4 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -2158,6 +2158,8 @@ >> >> #define _PIPEA_LINK_N1 0x60044 >> #define _PIPEB_LINK_N1 0x61044 >> +#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24) >> +#define PIPE_LINK_N1_EXTENDED(val) REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val)) >> #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) >> >> #define _PIPEA_LINK_M2 0x60048
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 426074afef43..4b1bb1f43adb 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2633,9 +2633,12 @@ void intel_zero_m_n(struct intel_link_m_n *m_n) void intel_set_m_n(struct drm_i915_private *i915, const struct intel_link_m_n *m_n, + u8 link_n_ext, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg) { + u8 link_n = m_n->link_n; + intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); intel_de_write(i915, data_n_reg, m_n->data_n); intel_de_write(i915, link_m_reg, m_n->link_m); @@ -2643,7 +2646,11 @@ void intel_set_m_n(struct drm_i915_private *i915, * On BDW+ writing LINK_N arms the double buffered update * of all the M/N registers, so it must be written last. */ - intel_de_write(i915, link_n_reg, m_n->link_n); + + if (DISPLAY_VER(i915) >= 14 && link_n_ext) + link_n |= PIPE_LINK_N1_EXTENDED(link_n_ext); + + intel_de_write(i915, link_n_reg, link_n); } bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, @@ -2663,13 +2670,13 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; if (DISPLAY_VER(dev_priv) >= 5) - intel_set_m_n(dev_priv, m_n, + intel_set_m_n(dev_priv, m_n, 0, PIPE_DATA_M1(dev_priv, transcoder), PIPE_DATA_N1(dev_priv, transcoder), PIPE_LINK_M1(dev_priv, transcoder), PIPE_LINK_N1(dev_priv, transcoder)); else - intel_set_m_n(dev_priv, m_n, + intel_set_m_n(dev_priv, m_n, 0, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); } @@ -2683,7 +2690,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) return; - intel_set_m_n(dev_priv, m_n, + intel_set_m_n(dev_priv, m_n, 0, PIPE_DATA_M2(dev_priv, transcoder), PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(dev_priv, transcoder), @@ -3351,7 +3358,11 @@ void intel_get_m_n(struct drm_i915_private *i915, i915_reg_t link_m_reg, i915_reg_t link_n_reg) { m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; - m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; + m_n->link_n = intel_de_read(i915, link_n_reg); + + if (DISPLAY_VER(i915) < 14) + m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK; + m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 4bdb48084cab..3b12d7f7c6c3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -473,7 +473,7 @@ bool intel_fuzzy_clock_check(int clock1, int clock2); void intel_zero_m_n(struct intel_link_m_n *m_n); void intel_set_m_n(struct drm_i915_private *i915, - const struct intel_link_m_n *m_n, + const struct intel_link_m_n *m_n, u8 link_n_ext, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg); void intel_get_m_n(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index f13ab680c2cf..74bc4de6d123 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -178,7 +178,7 @@ static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - intel_set_m_n(dev_priv, m_n, + intel_set_m_n(dev_priv, m_n, 0, PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); } @@ -189,7 +189,7 @@ static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - intel_set_m_n(dev_priv, m_n, + intel_set_m_n(dev_priv, m_n, 0, PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7396fc630e29..a770b5dbf5e4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2158,6 +2158,8 @@ #define _PIPEA_LINK_N1 0x60044 #define _PIPEB_LINK_N1 0x61044 +#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24) +#define PIPE_LINK_N1_EXTENDED(val) REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val)) #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) #define _PIPEA_LINK_M2 0x60048
LINK_N register has bits 31:24 for extended link N value used for HDMI2.1 and for an alternate mode of operation of DP TG DDA (Bspec:50488). Add support for these extra bits. v2: Drop extra link_n_ext member. (Jani) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++----- drivers/gpu/drm/i915/display/intel_display.h | 2 +- .../gpu/drm/i915/display/intel_pch_display.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 4 files changed, 21 insertions(+), 8 deletions(-)