| Message ID | 20240913074325.239390-7-billy_tsai@aspeedtech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Aspeed G7 gpio support | expand |
On Fri, 2024-09-13 at 15:43 +0800, Billy Tsai wrote: > Performing a dummy read ensures that the register write operation is fully > completed, mitigating any potential bus delays that could otherwise impact > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on > a delay function to ensure the clock frequency does not exceed 1 MHz. > However, this can lead to rapid toggling of the GPIO because the write > operation is POSTed and does not wait for a bus acknowledgment. > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> ... are you aware of any other driver concerns of a similar nature wrt the architecture of the SoCs?
> > Performing a dummy read ensures that the register write operation is fully > > completed, mitigating any potential bus delays that could otherwise impact > > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to > > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application > > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on > > a delay function to ensure the clock frequency does not exceed 1 MHz. > > However, this can lead to rapid toggling of the GPIO because the write > > operation is POSTed and does not wait for a bus acknowledgment. > > > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> > ... are you aware of any other driver concerns of a similar nature wrt > the architecture of the SoCs? No, we are only aware of this issue with the GPIO controller, which affects the output pin behavior immediately after register write.
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index d322c03481a8..d1e61ee48da2 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -406,6 +406,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, gpio->dcache[GPIO_BANK(offset)] = reg; gpio->config->llops->reg_bits_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bits_read(gpio, offset, reg_val); } static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+)