| Message ID | 20240903083528.2182190-1-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | support I2C for AST2700 | expand |
On 9/3/24 10:35, Jamin Lin wrote: > v1: > - support I2C for AST2700 > > v2: > - fix review issues and add reviewer suggestion > - update avocado test case for AST2700 I2C > - support i2c bus pool > > v3: > - update commit messages and commit title > - update API to get the device irq > > Jamin Lin (11): > hw/i2c/aspeed: Support discontinuous register memory region of I2C bus > hw/i2c/aspeed: Introduce a new bus pool buffer attribute in > AspeedI2Cbus > hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C > bus > hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in > AspeedI2Cbus > hw/i2c/aspeed: Add AST2700 support > hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses > hw/i2c/aspeed: Add support for 64 bit addresses > aspeed/soc: Introduce a new API to get the device irq > aspeed/soc: Support I2C for AST2700 > aspeed: Add tmp105 in i2c bus 0 for AST2700 > machine_aspeed.py: Update to test I2C for AST2700 > > hw/arm/aspeed.c | 10 ++ > hw/arm/aspeed_ast27x0.c | 45 +++++ > hw/i2c/aspeed_i2c.c | 310 ++++++++++++++++++++++++++++---- > include/hw/i2c/aspeed_i2c.h | 28 ++- > tests/avocado/machine_aspeed.py | 16 ++ > 5 files changed, 362 insertions(+), 47 deletions(-) > Applied to aspeed-next. Thanks, C.
Hi Cedric, > Subject: Re: [SPAM] [PATCH v3 00/11] support I2C for AST2700 > > On 9/3/24 10:35, Jamin Lin wrote: > > v1: > > - support I2C for AST2700 > > > > v2: > > - fix review issues and add reviewer suggestion > > - update avocado test case for AST2700 I2C > > - support i2c bus pool > > > > v3: > > - update commit messages and commit title > > - update API to get the device irq > > > > Jamin Lin (11): > > hw/i2c/aspeed: Support discontinuous register memory region of I2C bus > > hw/i2c/aspeed: Introduce a new bus pool buffer attribute in > > AspeedI2Cbus > > hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C > > bus > > hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in > > AspeedI2Cbus > > hw/i2c/aspeed: Add AST2700 support > > hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses > > hw/i2c/aspeed: Add support for 64 bit addresses > > aspeed/soc: Introduce a new API to get the device irq > > aspeed/soc: Support I2C for AST2700 > > aspeed: Add tmp105 in i2c bus 0 for AST2700 > > machine_aspeed.py: Update to test I2C for AST2700 > > > > hw/arm/aspeed.c | 10 ++ > > hw/arm/aspeed_ast27x0.c | 45 +++++ > > hw/i2c/aspeed_i2c.c | 310 > ++++++++++++++++++++++++++++---- > > include/hw/i2c/aspeed_i2c.h | 28 ++- > > tests/avocado/machine_aspeed.py | 16 ++ > > 5 files changed, 362 insertions(+), 47 deletions(-) > > > > > > Applied to aspeed-next. > > Thanks, > Thanks for your kindly support. Just want you to know that I and Troy are working on the following tasks for AST2700. 1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35) 2. Support GPIO. After we finish above tasks, we will upstream QEMU and send our patches. Thanks-Jamin > C. >
Hello Jamin, > Just want you to know that I and Troy are working on the following tasks for AST2700. > 1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35) Oh nice. This is a good topic for heterogeneous machines ! > 2. Support GPIO. > > After we finish above tasks, we will upstream QEMU and send our patches. There is also this issue we discussed privately on SPI write transactions failing on the AST27000. It looked related to aspeed_smc_do_snoop() but we don't have a good fix yet. When time permits, could you please open a gitlab issue with your findings and logs, so that we don't forget. Thanks, C.
Hi Cedric, > Subject: Re: [SPAM] [PATCH v3 00/11] support I2C for AST2700 > > Hello Jamin, > > > Just want you to know that I and Troy are working on the following tasks for > AST2700. > > 1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35) > > Oh nice. This is a good topic for heterogeneous machines ! > > > 2. Support GPIO. > > > > After we finish above tasks, we will upstream QEMU and send our patches. > > > There is also this issue we discussed privately on SPI write transactions failing > on the AST27000. It looked related to > aspeed_smc_do_snoop() but we don't have a good fix yet. > > When time permits, could you please open a gitlab issue with your findings > and logs, so that we don't forget. > Thanks for reminding. Okay. I will open an issue here, https://gitlab.com/qemu-project/qemu/-/issues Thanks-Jamin > > Thanks, > > C. >
Hi Cédric, On Wed, Sep 4, 2024 at 3:29 PM Cédric Le Goater <clg@kaod.org> wrote: > > Hello Jamin, > > > Just want you to know that I and Troy are working on the following tasks for AST2700. > > 1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35) > > Oh nice. This is a good topic for heterogeneous machines ! The basic model for bootmcu(risc-v) is working now, but we're looking for a way to integrate sram/mmio/dram together. The ivshmem requires PCI, it might be too complicate for our use case. There is an ivshmem-flat probably more sutiable for us. [PATCH 0/4] Add ivshmem-flat device - Gustavo Romero (kernel.org) https://lore.kernel.org/qemu-devel/20231127052024.435743-1-gustavo.romero@linaro.org/ > > > 2. Support GPIO. > > > > After we finish above tasks, we will upstream QEMU and send our patches. > > > There is also this issue we discussed privately on SPI write > transactions failing on the AST27000. It looked related to > aspeed_smc_do_snoop() but we don't have a good fix yet. > > When time permits, could you please open a gitlab issue with > your findings and logs, so that we don't forget. > > > Thanks, > > C. > > Thanks, Troy Lee
Hello, On 9/4/24 11:01, Troy Lee wrote: > Hi Cédric, > > On Wed, Sep 4, 2024 at 3:29 PM Cédric Le Goater <clg@kaod.org> wrote: >> >> Hello Jamin, >> >>> Just want you to know that I and Troy are working on the following tasks for AST2700. >>> 1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35) >> >> Oh nice. This is a good topic for heterogeneous machines ! > > The basic model for bootmcu(risc-v) is working now, May be send that first. > but we're looking for a way > to integrate sram/mmio/dram together. Unfortunately, QEMU is not yet ready for heterogeneous architectures. > The ivshmem requires PCI, it might be > too complicate for our use case. There is an ivshmem-flat probably more > sutiable for us. > > [PATCH 0/4] Add ivshmem-flat device - Gustavo Romero (kernel.org) > https://lore.kernel.org/qemu-devel/20231127052024.435743-1-gustavo.romero@linaro.org/ I lack expertise in that area. Adding Gustavo. Thanks, C.
Hi Cedric, > Subject: RE: [SPAM] [PATCH v3 00/11] support I2C for AST2700 > > Hi Cedric, > > > Subject: Re: [SPAM] [PATCH v3 00/11] support I2C for AST2700 > > > > Hello Jamin, > > > > > Just want you to know that I and Troy are working on the following > > > tasks for > > AST2700. > > > 1. Support boot from bootmcu(riscv32) instead of u-boot(Cortex-A35) > > > > Oh nice. This is a good topic for heterogeneous machines ! > > > > > 2. Support GPIO. > > > > > > After we finish above tasks, we will upstream QEMU and send our patches. > > > > > > There is also this issue we discussed privately on SPI write > > transactions failing on the AST27000. It looked related to > > aspeed_smc_do_snoop() but we don't have a good fix yet. > > > > When time permits, could you please open a gitlab issue with your > > findings and logs, so that we don't forget. > > > Thanks for reminding. > > Okay. I will open an issue here, https://gitlab.com/qemu-project/qemu/-/issues > Thanks-Jamin > > Sorry, Due to my PTO. I will open an new issue and send a patch to fix this issue, soon. Thanks-Jamin > > Thanks, > > > > C. > >
v1: - support I2C for AST2700 v2: - fix review issues and add reviewer suggestion - update avocado test case for AST2700 I2C - support i2c bus pool v3: - update commit messages and commit title - update API to get the device irq Jamin Lin (11): hw/i2c/aspeed: Support discontinuous register memory region of I2C bus hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2Cbus hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C bus hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus hw/i2c/aspeed: Add AST2700 support hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses hw/i2c/aspeed: Add support for 64 bit addresses aspeed/soc: Introduce a new API to get the device irq aspeed/soc: Support I2C for AST2700 aspeed: Add tmp105 in i2c bus 0 for AST2700 machine_aspeed.py: Update to test I2C for AST2700 hw/arm/aspeed.c | 10 ++ hw/arm/aspeed_ast27x0.c | 45 +++++ hw/i2c/aspeed_i2c.c | 310 ++++++++++++++++++++++++++++---- include/hw/i2c/aspeed_i2c.h | 28 ++- tests/avocado/machine_aspeed.py | 16 ++ 5 files changed, 362 insertions(+), 47 deletions(-)