| Message ID | 20240916155119.14610-1-itachis@FreeBSD.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | bsd-user: Comprehensive RISCV Support | expand |
On 9/16/24 12:51 PM, Ajeet Singh wrote: > Key Changes Compared to Version 6: > Included "signal-common.h" in target_arch_cpu.h Thanks. This version is successfully compiling in a FreeBSD x86 host. Daniel > > Mark Corbin (15): > bsd-user: Implement RISC-V CPU initialization and main loop > bsd-user: Add RISC-V CPU execution loop and syscall handling > bsd-user: Implement RISC-V CPU register cloning and reset functions > bsd-user: Implement RISC-V TLS register setup > bsd-user: Add RISC-V ELF definitions and hardware capability detection > bsd-user: Define RISC-V register structures and register copying > bsd-user: Add RISC-V signal trampoline setup function > bsd-user: Implement RISC-V sysarch system call emulation > bsd-user: Add RISC-V thread setup and initialization support > bsd-user: Define RISC-V VM parameters and helper functions > bsd-user: Define RISC-V system call structures and constants > bsd-user: Define RISC-V signal handling structures and constants > bsd-user: Implement RISC-V signal trampoline setup functions > bsd-user: Implement 'get_mcontext' for RISC-V > bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV > > Warner Losh (2): > bsd-user: Add generic RISC-V64 target definitions > bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files > > bsd-user/riscv/signal.c | 170 ++++++++++++++++++++++++++ > bsd-user/riscv/target.h | 20 +++ > bsd-user/riscv/target_arch.h | 27 ++++ > bsd-user/riscv/target_arch_cpu.c | 29 +++++ > bsd-user/riscv/target_arch_cpu.h | 148 ++++++++++++++++++++++ > bsd-user/riscv/target_arch_elf.h | 42 +++++++ > bsd-user/riscv/target_arch_reg.h | 88 +++++++++++++ > bsd-user/riscv/target_arch_signal.h | 75 ++++++++++++ > bsd-user/riscv/target_arch_sigtramp.h | 41 +++++++ > bsd-user/riscv/target_arch_sysarch.h | 41 +++++++ > bsd-user/riscv/target_arch_thread.h | 47 +++++++ > bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++ > bsd-user/riscv/target_syscall.h | 38 ++++++ > configs/targets/riscv64-bsd-user.mak | 4 + > 14 files changed, 823 insertions(+) > create mode 100644 bsd-user/riscv/signal.c > create mode 100644 bsd-user/riscv/target.h > create mode 100644 bsd-user/riscv/target_arch.h > create mode 100644 bsd-user/riscv/target_arch_cpu.c > create mode 100644 bsd-user/riscv/target_arch_cpu.h > create mode 100644 bsd-user/riscv/target_arch_elf.h > create mode 100644 bsd-user/riscv/target_arch_reg.h > create mode 100644 bsd-user/riscv/target_arch_signal.h > create mode 100644 bsd-user/riscv/target_arch_sigtramp.h > create mode 100644 bsd-user/riscv/target_arch_sysarch.h > create mode 100644 bsd-user/riscv/target_arch_thread.h > create mode 100644 bsd-user/riscv/target_arch_vmparam.h > create mode 100644 bsd-user/riscv/target_syscall.h > create mode 100644 configs/targets/riscv64-bsd-user.mak >
On Tue, Sep 17, 2024 at 1:54 AM Ajeet Singh <itachis6234@gmail.com> wrote: > > Key Changes Compared to Version 6: > Included "signal-common.h" in target_arch_cpu.h > > Mark Corbin (15): > bsd-user: Implement RISC-V CPU initialization and main loop > bsd-user: Add RISC-V CPU execution loop and syscall handling > bsd-user: Implement RISC-V CPU register cloning and reset functions > bsd-user: Implement RISC-V TLS register setup > bsd-user: Add RISC-V ELF definitions and hardware capability detection > bsd-user: Define RISC-V register structures and register copying > bsd-user: Add RISC-V signal trampoline setup function > bsd-user: Implement RISC-V sysarch system call emulation > bsd-user: Add RISC-V thread setup and initialization support > bsd-user: Define RISC-V VM parameters and helper functions > bsd-user: Define RISC-V system call structures and constants > bsd-user: Define RISC-V signal handling structures and constants > bsd-user: Implement RISC-V signal trampoline setup functions > bsd-user: Implement 'get_mcontext' for RISC-V > bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV > > Warner Losh (2): > bsd-user: Add generic RISC-V64 target definitions > bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Thanks! Applied to riscv-to-apply.next Alistair > > bsd-user/riscv/signal.c | 170 ++++++++++++++++++++++++++ > bsd-user/riscv/target.h | 20 +++ > bsd-user/riscv/target_arch.h | 27 ++++ > bsd-user/riscv/target_arch_cpu.c | 29 +++++ > bsd-user/riscv/target_arch_cpu.h | 148 ++++++++++++++++++++++ > bsd-user/riscv/target_arch_elf.h | 42 +++++++ > bsd-user/riscv/target_arch_reg.h | 88 +++++++++++++ > bsd-user/riscv/target_arch_signal.h | 75 ++++++++++++ > bsd-user/riscv/target_arch_sigtramp.h | 41 +++++++ > bsd-user/riscv/target_arch_sysarch.h | 41 +++++++ > bsd-user/riscv/target_arch_thread.h | 47 +++++++ > bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++ > bsd-user/riscv/target_syscall.h | 38 ++++++ > configs/targets/riscv64-bsd-user.mak | 4 + > 14 files changed, 823 insertions(+) > create mode 100644 bsd-user/riscv/signal.c > create mode 100644 bsd-user/riscv/target.h > create mode 100644 bsd-user/riscv/target_arch.h > create mode 100644 bsd-user/riscv/target_arch_cpu.c > create mode 100644 bsd-user/riscv/target_arch_cpu.h > create mode 100644 bsd-user/riscv/target_arch_elf.h > create mode 100644 bsd-user/riscv/target_arch_reg.h > create mode 100644 bsd-user/riscv/target_arch_signal.h > create mode 100644 bsd-user/riscv/target_arch_sigtramp.h > create mode 100644 bsd-user/riscv/target_arch_sysarch.h > create mode 100644 bsd-user/riscv/target_arch_thread.h > create mode 100644 bsd-user/riscv/target_arch_vmparam.h > create mode 100644 bsd-user/riscv/target_syscall.h > create mode 100644 configs/targets/riscv64-bsd-user.mak > > -- > 2.34.1 > >