| Message ID | 20240902-x1e80100-crd-dts-add-external-dp-support-v1-1-899c264c0eb7@linaro.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: Add external DP support to CRD and T14s | expand |
On Mon, Sep 02, 2024 at 06:01:35PM GMT, Abel Vesa wrote: > The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, > all of them supporting external DP altmode. Between each QMP > combo PHY and the corresponding Type-C port, sits one Parade PS8830 > retimer which handles both orientation and SBU muxing. Add nodes for > each retimer, fix the graphs between connectors and the PHYs accordingly, > add the voltage regulators needed by each retimer and then enable all > 3 remaining DPUs. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 414 +++++++++++++++++++++++++++++- > 1 file changed, 408 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts > index 10b28d870f08..6dfc85eda354 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts > +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts [skipped] > @@ -709,6 +861,163 @@ keyboard@3a { > }; > }; > > +&i2c1 { > + clock-frequency = <400000>; > + > + status = "okay"; > + > + typec-mux@8 { > + compatible = "parade,ps8830"; > + reg = <0x08>; > + > + clocks = <&rpmhcc RPMH_RF_CLK5>; > + clock-names = "xo"; > + > + vdd15-supply = <&vreg_rtmr2_1p15>; > + vdd18-supply = <&vreg_rtmr2_1p8>; > + vdd33-supply = <&vreg_rtmr2_3p3>; > + > + reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>; > + > + orientation-switch; > + retimer-switch; Doesn't it need to listen to mode switching events? 4-lane DP vs 2/2-lane DP + USB3 requires propagating of the altmode events to the QMP PHY, see the original 4-lane series. > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + retimer_ss2_ss_out: endpoint { > + remote-endpoint = <&pmic_glink_ss2_ss_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + retimer_ss2_ss_in: endpoint { > + remote-endpoint = <&usb_1_ss2_qmpphy_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + > + retimer_ss2_con_sbu_out: endpoint { > + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; > + }; > + }; > + }; > + }; > +}; > + > @@ -1164,7 +1566,7 @@ &usb_1_ss0_dwc3_hs { > }; > > &usb_1_ss0_qmpphy_out { > - remote-endpoint = <&pmic_glink_ss0_ss_in>; > + remote-endpoint = <&retimer_ss0_ss_in>; > }; orientation-switch and mode-switch for the QMP PHY? > > &usb_1_ss1_hsphy { > @@ -1196,7 +1598,7 @@ &usb_1_ss1_dwc3_hs { > }; > > &usb_1_ss1_qmpphy_out { > - remote-endpoint = <&pmic_glink_ss1_ss_in>; > + remote-endpoint = <&retimer_ss1_ss_in>; > }; > > &usb_1_ss2_hsphy { > @@ -1228,5 +1630,5 @@ &usb_1_ss2_dwc3_hs { > }; > > &usb_1_ss2_qmpphy_out { > - remote-endpoint = <&pmic_glink_ss2_ss_in>; > + remote-endpoint = <&retimer_ss2_ss_in>; > }; > > -- > 2.34.1 >
On 2.09.2024 8:54 PM, Dmitry Baryshkov wrote: > On Mon, Sep 02, 2024 at 06:01:35PM GMT, Abel Vesa wrote: >> The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, >> all of them supporting external DP altmode. Between each QMP >> combo PHY and the corresponding Type-C port, sits one Parade PS8830 >> retimer which handles both orientation and SBU muxing. Add nodes for >> each retimer, fix the graphs between connectors and the PHYs accordingly, >> add the voltage regulators needed by each retimer and then enable all >> 3 remaining DPUs. >> >> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >> --- [...] > >> @@ -1164,7 +1566,7 @@ &usb_1_ss0_dwc3_hs { >> }; >> >> &usb_1_ss0_qmpphy_out { >> - remote-endpoint = <&pmic_glink_ss0_ss_in>; >> + remote-endpoint = <&retimer_ss0_ss_in>; >> }; > > orientation-switch https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?h=for-next&id=17c5909f53e01c151c91f66949a9c4f191756bae > and mode-switch for the QMP PHY? Oops! Looks like adding it and fixing some bugs in the qmpphy driver makes usb+dp work every now and then.. Konrad
On Mon, Sep 02, 2024 at 06:01:35PM +0300, Abel Vesa wrote: > The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, > all of them supporting external DP altmode. Between each QMP > combo PHY and the corresponding Type-C port, sits one Parade PS8830 > retimer which handles both orientation and SBU muxing. Add nodes for > each retimer, fix the graphs between connectors and the PHYs accordingly, > add the voltage regulators needed by each retimer and then enable all > 3 remaining DPUs. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 414 +++++++++++++++++++++++++++++- > 1 file changed, 408 insertions(+), 6 deletions(-) > @@ -288,6 +312,134 @@ vreg_edp_3p3: regulator-edp-3p3 { > regulator-boot-on; > }; > > + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { > + compatible = "regulator-fixed"; > + > + regulator-name = "VREG_RTMR0_1P15"; > + regulator-min-microvolt = <1150000>; > + regulator-max-microvolt = <1150000>; > + > + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + > + pinctrl-0 = <&rtmr0_1p15_reg_en>; > + pinctrl-names = "default"; > + }; > + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { > + compatible = "regulator-fixed"; > + > + regulator-name = "VREG_RTMR2_3P3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + > + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&rtmr2_3p3_reg_en>; > + }; > + > + > + Double stray newline. Also move these nodes below the nvme one to maintain sort order. > vreg_nvme: regulator-nvme { > compatible = "regulator-fixed"; > > @@ -709,6 +861,163 @@ keyboard@3a { > }; > }; > +&i2c7 { > + clock-frequency = <400000>; > + > + status = "okay"; > + > + typec-mux@8 { > + compatible = "parade,ps8830"; > + reg = <0x8>; > + > + clocks = <&rpmhcc RPMH_RF_CLK4>; > + clock-names = "xo"; > + > + vdd15-supply = <&vreg_rtmr1_1p15>; > + vdd18-supply = <&vreg_rtmr1_1p8>; > + vdd33-supply = <&vreg_rtmr1_3p3>; > + > + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; > + > + retimer-switch; > + orientation-switch; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + retimer_ss1_ss_out: endpoint { > + remote-endpoint = <&pmic_glink_ss1_ss_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + retimer_ss1_ss_in: endpoint { > + remote-endpoint = <&usb_1_ss1_qmpphy_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + > + retimer_ss1_con_sbu_out: endpoint { > + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; > + }; > + }; > + Stray newline. > + }; > + }; > +}; > +&pm8550_gpios { > + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { > + pins = "gpio11"; > + function = "func1"; > + input-disable; > + output-enable; > + }; > +}; > + > +&pm8550ve_8_gpios { > + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { > + pins = "gpio8"; > + function = "func1"; > + input-disable; > + output-enable; > + }; > +}; > + > +&pm8550ve_9_gpios { > + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { > + pins = "gpio8"; > + function = "func1"; > + input-disable; > + output-enable; > + }; > +}; Shouldn't you specify the drive strength here as well? (Same on T14s). Johan
On 24-09-03 09:09:52, Johan Hovold wrote: > On Mon, Sep 02, 2024 at 06:01:35PM +0300, Abel Vesa wrote: > > The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, > > all of them supporting external DP altmode. Between each QMP > > combo PHY and the corresponding Type-C port, sits one Parade PS8830 > > retimer which handles both orientation and SBU muxing. Add nodes for > > each retimer, fix the graphs between connectors and the PHYs accordingly, > > add the voltage regulators needed by each retimer and then enable all > > 3 remaining DPUs. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 414 +++++++++++++++++++++++++++++- > > 1 file changed, 408 insertions(+), 6 deletions(-) > > > @@ -288,6 +312,134 @@ vreg_edp_3p3: regulator-edp-3p3 { > > regulator-boot-on; > > }; > > > > + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { > > + compatible = "regulator-fixed"; > > + > > + regulator-name = "VREG_RTMR0_1P15"; > > + regulator-min-microvolt = <1150000>; > > + regulator-max-microvolt = <1150000>; > > + > > + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + > > + pinctrl-0 = <&rtmr0_1p15_reg_en>; > > + pinctrl-names = "default"; > > + }; > > > + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { > > + compatible = "regulator-fixed"; > > + > > + regulator-name = "VREG_RTMR2_3P3"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + > > + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + > > + pinctrl-names = "default"; > > + pinctrl-0 = <&rtmr2_3p3_reg_en>; > > + }; > > + > > + > > + > > Double stray newline. > > Also move these nodes below the nvme one to maintain sort order. > Will do. > > vreg_nvme: regulator-nvme { > > compatible = "regulator-fixed"; > > > > @@ -709,6 +861,163 @@ keyboard@3a { > > }; > > }; > > > +&i2c7 { > > + clock-frequency = <400000>; > > + > > + status = "okay"; > > + > > + typec-mux@8 { > > + compatible = "parade,ps8830"; > > + reg = <0x8>; > > + > > + clocks = <&rpmhcc RPMH_RF_CLK4>; > > + clock-names = "xo"; > > + > > + vdd15-supply = <&vreg_rtmr1_1p15>; > > + vdd18-supply = <&vreg_rtmr1_1p8>; > > + vdd33-supply = <&vreg_rtmr1_3p3>; > > + > > + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; > > + > > + retimer-switch; > > + orientation-switch; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + > > + retimer_ss1_ss_out: endpoint { > > + remote-endpoint = <&pmic_glink_ss1_ss_in>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + > > + retimer_ss1_ss_in: endpoint { > > + remote-endpoint = <&usb_1_ss1_qmpphy_out>; > > + }; > > + }; > > + > > + port@2 { > > + reg = <2>; > > + > > + retimer_ss1_con_sbu_out: endpoint { > > + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; > > + }; > > + }; > > + > > Stray newline. > Will drop. > > + }; > > + }; > > +}; > > > +&pm8550_gpios { > > + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { > > + pins = "gpio11"; > > + function = "func1"; > > + input-disable; > > + output-enable; > > + }; > > +}; > > + > > +&pm8550ve_8_gpios { > > + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { > > + pins = "gpio8"; > > + function = "func1"; > > + input-disable; > > + output-enable; > > + }; > > +}; > > + > > +&pm8550ve_9_gpios { > > + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { > > + pins = "gpio8"; > > + function = "func1"; > > + input-disable; > > + output-enable; > > + }; > > +}; > > Shouldn't you specify the drive strength here as well? (Same on T14s). > Will do. > Johan Thanks for reviewing. Abel
On 24-09-02 21:54:58, Dmitry Baryshkov wrote: > On Mon, Sep 02, 2024 at 06:01:35PM GMT, Abel Vesa wrote: > > The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, > > all of them supporting external DP altmode. Between each QMP > > combo PHY and the corresponding Type-C port, sits one Parade PS8830 > > retimer which handles both orientation and SBU muxing. Add nodes for > > each retimer, fix the graphs between connectors and the PHYs accordingly, > > add the voltage regulators needed by each retimer and then enable all > > 3 remaining DPUs. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 414 +++++++++++++++++++++++++++++- > > 1 file changed, 408 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts > > index 10b28d870f08..6dfc85eda354 100644 > > --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts > > +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts > > [skipped] > > > > @@ -709,6 +861,163 @@ keyboard@3a { > > }; > > }; > > > > +&i2c1 { > > + clock-frequency = <400000>; > > + > > + status = "okay"; > > + > > + typec-mux@8 { > > + compatible = "parade,ps8830"; > > + reg = <0x08>; > > + > > + clocks = <&rpmhcc RPMH_RF_CLK5>; > > + clock-names = "xo"; > > + > > + vdd15-supply = <&vreg_rtmr2_1p15>; > > + vdd18-supply = <&vreg_rtmr2_1p8>; > > + vdd33-supply = <&vreg_rtmr2_3p3>; > > + > > + reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>; > > + > > + orientation-switch; > > + retimer-switch; > > Doesn't it need to listen to mode switching events? 4-lane DP vs > 2/2-lane DP + USB3 requires propagating of the altmode events to the QMP > PHY, see the original 4-lane series. The mode is passed through the retimer state as well, isn't it? > > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + > > + retimer_ss2_ss_out: endpoint { > > + remote-endpoint = <&pmic_glink_ss2_ss_in>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + > > + retimer_ss2_ss_in: endpoint { > > + remote-endpoint = <&usb_1_ss2_qmpphy_out>; > > + }; > > + }; > > + > > + port@2 { > > + reg = <2>; > > + > > + retimer_ss2_con_sbu_out: endpoint { > > + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; > > + }; > > + }; > > + }; > > + }; > > +}; > > + > > > > @@ -1164,7 +1566,7 @@ &usb_1_ss0_dwc3_hs { > > }; > > > > &usb_1_ss0_qmpphy_out { > > - remote-endpoint = <&pmic_glink_ss0_ss_in>; > > + remote-endpoint = <&retimer_ss0_ss_in>; > > }; > > orientation-switch and mode-switch for the QMP PHY? orientation-switch is already in the SoC dtsi nodes. But the qmp phy doesn't currently support mode switching. Right? > > > > > &usb_1_ss1_hsphy { > > @@ -1196,7 +1598,7 @@ &usb_1_ss1_dwc3_hs { > > }; > > > > &usb_1_ss1_qmpphy_out { > > - remote-endpoint = <&pmic_glink_ss1_ss_in>; > > + remote-endpoint = <&retimer_ss1_ss_in>; > > }; > > > > &usb_1_ss2_hsphy { > > @@ -1228,5 +1630,5 @@ &usb_1_ss2_dwc3_hs { > > }; > > > > &usb_1_ss2_qmpphy_out { > > - remote-endpoint = <&pmic_glink_ss2_ss_in>; > > + remote-endpoint = <&retimer_ss2_ss_in>; > > }; > > > > -- > > 2.34.1 > > > > -- > With best wishes > Dmitry Thanks for reviewing. Abel
On Tue, 24 Sept 2024 at 13:08, Abel Vesa <abel.vesa@linaro.org> wrote: > > On 24-09-02 21:54:58, Dmitry Baryshkov wrote: > > On Mon, Sep 02, 2024 at 06:01:35PM GMT, Abel Vesa wrote: > > > The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, > > > all of them supporting external DP altmode. Between each QMP > > > combo PHY and the corresponding Type-C port, sits one Parade PS8830 > > > retimer which handles both orientation and SBU muxing. Add nodes for > > > each retimer, fix the graphs between connectors and the PHYs accordingly, > > > add the voltage regulators needed by each retimer and then enable all > > > 3 remaining DPUs. > > > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > > --- > > > arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 414 +++++++++++++++++++++++++++++- > > > 1 file changed, 408 insertions(+), 6 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts > > > index 10b28d870f08..6dfc85eda354 100644 > > > --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts > > > +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts > > > > [skipped] > > > > > > > @@ -709,6 +861,163 @@ keyboard@3a { > > > }; > > > }; > > > > > > +&i2c1 { > > > + clock-frequency = <400000>; > > > + > > > + status = "okay"; > > > + > > > + typec-mux@8 { > > > + compatible = "parade,ps8830"; > > > + reg = <0x08>; > > > + > > > + clocks = <&rpmhcc RPMH_RF_CLK5>; > > > + clock-names = "xo"; > > > + > > > + vdd15-supply = <&vreg_rtmr2_1p15>; > > > + vdd18-supply = <&vreg_rtmr2_1p8>; > > > + vdd33-supply = <&vreg_rtmr2_3p3>; > > > + > > > + reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>; > > > + > > > + orientation-switch; > > > + retimer-switch; > > > > Doesn't it need to listen to mode switching events? 4-lane DP vs > > 2/2-lane DP + USB3 requires propagating of the altmode events to the QMP > > PHY, see the original 4-lane series. > > The mode is passed through the retimer state as well, isn't it? ack. > > > > > > + > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + port@0 { > > > + reg = <0>; > > > + > > > + retimer_ss2_ss_out: endpoint { > > > + remote-endpoint = <&pmic_glink_ss2_ss_in>; > > > + }; > > > + }; > > > + > > > + port@1 { > > > + reg = <1>; > > > + > > > + retimer_ss2_ss_in: endpoint { > > > + remote-endpoint = <&usb_1_ss2_qmpphy_out>; > > > + }; > > > + }; > > > + > > > + port@2 { > > > + reg = <2>; > > > + > > > + retimer_ss2_con_sbu_out: endpoint { > > > + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; > > > + }; > > > + }; > > > + }; > > > + }; > > > +}; > > > + > > > > > > > @@ -1164,7 +1566,7 @@ &usb_1_ss0_dwc3_hs { > > > }; > > > > > > &usb_1_ss0_qmpphy_out { > > > - remote-endpoint = <&pmic_glink_ss0_ss_in>; > > > + remote-endpoint = <&retimer_ss0_ss_in>; > > > }; > > > > orientation-switch and mode-switch for the QMP PHY? > > orientation-switch is already in the SoC dtsi nodes. > > But the qmp phy doesn't currently support mode switching. Right? Yeah, we didn't land that patchset :-( > > > > > > > > > &usb_1_ss1_hsphy { > > > @@ -1196,7 +1598,7 @@ &usb_1_ss1_dwc3_hs { > > > }; > > > > > > &usb_1_ss1_qmpphy_out { > > > - remote-endpoint = <&pmic_glink_ss1_ss_in>; > > > + remote-endpoint = <&retimer_ss1_ss_in>; > > > }; > > > > > > &usb_1_ss2_hsphy { > > > @@ -1228,5 +1630,5 @@ &usb_1_ss2_dwc3_hs { > > > }; > > > > > > &usb_1_ss2_qmpphy_out { > > > - remote-endpoint = <&pmic_glink_ss2_ss_in>; > > > + remote-endpoint = <&retimer_ss2_ss_in>; > > > }; > > > > > > -- > > > 2.34.1 > > > > > > > -- > > With best wishes > > Dmitry > > Thanks for reviewing. > > Abel
On Mon, Sep 02, 2024 at 06:01:35PM +0300, Abel Vesa wrote: > The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, > all of them supporting external DP altmode. Between each QMP > combo PHY and the corresponding Type-C port, sits one Parade PS8830 > retimer which handles both orientation and SBU muxing. Add nodes for > each retimer, fix the graphs between connectors and the PHYs accordingly, > add the voltage regulators needed by each retimer and then enable all > 3 remaining DPUs. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { > + compatible = "regulator-fixed"; > + > + regulator-name = "VREG_RTMR0_1P15"; > + regulator-min-microvolt = <1150000>; > + regulator-max-microvolt = <1150000>; > + > + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; When reviewing the schematics yesterday, I noticed that this is wrong and that this enable GPIO comes from pmc8380_5_gpios. Fortunately the above gpio is unused, but please double check the other as well (I think the rest are correct). You need to fix the pincfg as well. > + enable-active-high; > + > + pinctrl-0 = <&rtmr0_1p15_reg_en>; Please rename the enable pins according to the schematics too (e.g. "usb0_pwr_1p15_en"). > + pinctrl-names = "default"; > + }; > +&i2c1 { > + clock-frequency = <400000>; > + > + status = "okay"; > + > + typec-mux@8 { > + compatible = "parade,ps8830"; > + reg = <0x08>; > + > + clocks = <&rpmhcc RPMH_RF_CLK5>; > + clock-names = "xo"; > + > + vdd15-supply = <&vreg_rtmr2_1p15>; > + vdd18-supply = <&vreg_rtmr2_1p8>; > + vdd33-supply = <&vreg_rtmr2_3p3>; > + > + reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>; As I mentioned elsewhere, the reset lines are active low. > +&pm8550_gpios { > + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { > + pins = "gpio11"; > + function = "func1"; And this should be "normal" for gpio function, right? Same below. > + input-disable; > + output-enable; And I don't think you need to provide these. > + }; > +}; Johan
On Mon, Sep 02, 2024 at 06:01:35PM +0300, Abel Vesa wrote: > The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, > all of them supporting external DP altmode. Between each QMP > combo PHY and the corresponding Type-C port, sits one Parade PS8830 > retimer which handles both orientation and SBU muxing. Add nodes for > each retimer, fix the graphs between connectors and the PHYs accordingly, > add the voltage regulators needed by each retimer and then enable all > 3 remaining DPUs. > +&i2c1 { > + clock-frequency = <400000>; > + > + status = "okay"; > + > + typec-mux@8 { > + compatible = "parade,ps8830"; > + reg = <0x08>; > + > + clocks = <&rpmhcc RPMH_RF_CLK5>; > + clock-names = "xo"; > + > + vdd15-supply = <&vreg_rtmr2_1p15>; > + vdd18-supply = <&vreg_rtmr2_1p8>; > + vdd33-supply = <&vreg_rtmr2_3p3>; > + > + reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>; pincfg missing > +&i2c3 { > + clock-frequency = <400000>; > + > + status = "okay"; > + > + typec-mux@8 { > + compatible = "parade,ps8830"; > + reg = <0x08>; > + > + clocks = <&rpmhcc RPMH_RF_CLK3>; > + clock-names = "xo"; > + > + vdd15-supply = <&vreg_rtmr0_1p15>; > + vdd18-supply = <&vreg_rtmr0_1p8>; > + vdd33-supply = <&vreg_rtmr0_3p3>; > + > + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>; Same here. > +&i2c7 { > + clock-frequency = <400000>; > + > + status = "okay"; > + > + typec-mux@8 { > + compatible = "parade,ps8830"; > + reg = <0x8>; > + > + clocks = <&rpmhcc RPMH_RF_CLK4>; > + clock-names = "xo"; > + > + vdd15-supply = <&vreg_rtmr1_1p15>; > + vdd18-supply = <&vreg_rtmr1_1p8>; > + vdd33-supply = <&vreg_rtmr1_3p3>; > + > + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; And here. Johan
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 10b28d870f08..6dfc85eda354 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -99,7 +99,15 @@ port@1 { reg = <1>; pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; }; }; }; @@ -128,7 +136,15 @@ port@1 { reg = <1>; pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; }; }; }; @@ -157,7 +173,15 @@ port@1 { reg = <1>; pmic_glink_ss2_ss_in: endpoint { - remote-endpoint = <&usb_1_ss2_qmpphy_out>; + remote-endpoint = <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss2_con_sbu_out>; }; }; }; @@ -288,6 +312,134 @@ vreg_edp_3p3: regulator-edp-3p3 { regulator-boot-on; }; + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p15_reg_en>; + pinctrl-names = "default"; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p8_reg_en>; + pinctrl-names = "default"; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_3p3_reg_en>; + pinctrl-names = "default"; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_1p15_reg_en>; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_1p8_reg_en>; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr1_3p3_reg_en>; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr2_1p15_reg_en>; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr2_1p8_reg_en>; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rtmr2_3p3_reg_en>; + }; + + + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -709,6 +861,163 @@ keyboard@3a { }; }; +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK5>; + clock-names = "xo"; + + vdd15-supply = <&vreg_rtmr2_1p15>; + vdd18-supply = <&vreg_rtmr2_1p8>; + vdd33-supply = <&vreg_rtmr2_3p3>; + + reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + clock-names = "xo"; + + vdd15-supply = <&vreg_rtmr0_1p15>; + vdd18-supply = <&vreg_rtmr0_1p8>; + vdd33-supply = <&vreg_rtmr0_3p3>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + clock-names = "xo"; + + vdd15-supply = <&vreg_rtmr1_1p15>; + vdd18-supply = <&vreg_rtmr1_1p8>; + vdd33-supply = <&vreg_rtmr1_3p3>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + + }; + }; +}; + &i2c8 { clock-frequency = <400000>; @@ -756,6 +1065,30 @@ &mdss { status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1 2 3>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + data-lanes = <0 1 2 3>; +}; + &mdss_dp3 { compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; @@ -854,6 +1187,33 @@ &pcie6a_phy { status = "okay"; }; +&pm8550_gpios { + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { + pins = "gpio11"; + function = "func1"; + input-disable; + output-enable; + }; +}; + +&pm8550ve_8_gpios { + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { + pins = "gpio8"; + function = "func1"; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { + pins = "gpio8"; + function = "func1"; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins = "gpio4"; @@ -1093,6 +1453,48 @@ wake-n-pins { }; }; + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_1p15_reg_en: rtmr2-1p15-reg-en-state { + pins = "gpio189"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_1p8_reg_en: rtmr2-1p8-reg-en-state { + pins = "gpio126"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_3p3_reg_en: rtmr2-3p3-reg-en-state { + pins = "gpio187"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + tpad_default: tpad-default-state { pins = "gpio3"; function = "gpio"; @@ -1164,7 +1566,7 @@ &usb_1_ss0_dwc3_hs { }; &usb_1_ss0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss0_ss_in>; + remote-endpoint = <&retimer_ss0_ss_in>; }; &usb_1_ss1_hsphy { @@ -1196,7 +1598,7 @@ &usb_1_ss1_dwc3_hs { }; &usb_1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss1_ss_in>; + remote-endpoint = <&retimer_ss1_ss_in>; }; &usb_1_ss2_hsphy { @@ -1228,5 +1630,5 @@ &usb_1_ss2_dwc3_hs { }; &usb_1_ss2_qmpphy_out { - remote-endpoint = <&pmic_glink_ss2_ss_in>; + remote-endpoint = <&retimer_ss2_ss_in>; };
The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports, all of them supporting external DP altmode. Between each QMP combo PHY and the corresponding Type-C port, sits one Parade PS8830 retimer which handles both orientation and SBU muxing. Add nodes for each retimer, fix the graphs between connectors and the PHYs accordingly, add the voltage regulators needed by each retimer and then enable all 3 remaining DPUs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 414 +++++++++++++++++++++++++++++- 1 file changed, 408 insertions(+), 6 deletions(-)