| Message ID | 20240923-pcie_ep_range-v2-4-78d2ea434d9f@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices | expand |
> -----Original Message----- > From: Frank Li <frank.li@nxp.com> > Sent: 2024年9月24日 2:59 > To: Lorenzo Pieralisi <lpieralisi@kernel.org>; Krzysztof Wilczyński > <kw@linux.com>; Manivannan Sadhasivam > <manivannan.sadhasivam@linaro.org>; Rob Herring <robh@kernel.org>; > Bjorn Helgaas <bhelgaas@google.com>; Krzysztof Kozlowski > <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Abraham I > <kishon@kernel.org>; Saravana Kannan <saravanak@google.com>; Jingoo > Han <jingoohan1@gmail.com>; Gustavo Pimentel > <gustavo.pimentel@synopsys.com>; Jesper Nilsson > <jesper.nilsson@axis.com>; Hongxing Zhu <hongxing.zhu@nxp.com>; Lucas > Stach <l.stach@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>; > Sascha Hauer <s.hauer@pengutronix.de>; Pengutronix Kernel Team > <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com> > Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-kernel@axis.com; > linux-arm-kernel@lists.infradead.org; imx@lists.linux.dev; Krzysztof > Wilczyński <kwilczynski@kernel.org>; Frank Li <frank.li@nxp.com> > Subject: [PATCH v2 4/4] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support > > Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe > Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the > CPU addresses. The DesignWare (DWC) driver already handles this in the > common code. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Best Regards Richard Zhu > --- > drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c > b/drivers/pci/controller/dwc/pci-imx6.c > index bdc2b372e6c13..1e58c24137e7f 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -70,6 +70,7 @@ enum imx_pcie_variants { > IMX8MQ_EP, > IMX8MM_EP, > IMX8MP_EP, > + IMX8Q_EP, > IMX95_EP, > }; > > @@ -1079,6 +1080,16 @@ static const struct pci_epc_features > imx8m_pcie_epc_features = { > .align = SZ_64K, > }; > > +static const struct pci_epc_features imx8q_pcie_epc_features = { > + .linkup_notifier = false, > + .msi_capable = true, > + .msix_capable = false, > + .bar[BAR_1] = { .type = BAR_RESERVED, }, > + .bar[BAR_3] = { .type = BAR_RESERVED, }, > + .bar[BAR_5] = { .type = BAR_RESERVED, }, > + .align = SZ_64K, > +}; > + > /* > * BAR# | Default BAR enable | Default BAR Type | Default BAR Size > | BAR Sizing Scheme > * > ============================================================== > ================================== > @@ -1645,6 +1656,14 @@ static const struct imx_pcie_drvdata drvdata[] = { > .epc_features = &imx8m_pcie_epc_features, > .enable_ref_clk = imx8mm_pcie_enable_ref_clk, > }, > + [IMX8Q_EP] = { > + .variant = IMX8Q_EP, > + .flags = IMX_PCIE_FLAG_HAS_PHYDRV, > + .mode = DW_PCIE_EP_TYPE, > + .epc_features = &imx8q_pcie_epc_features, > + .clk_names = imx8q_clks, > + .clks_cnt = ARRAY_SIZE(imx8q_clks), > + }, > [IMX95_EP] = { > .variant = IMX95_EP, > .flags = IMX_PCIE_FLAG_HAS_SERDES | > @@ -1674,6 +1693,7 @@ static const struct of_device_id > imx_pcie_of_match[] = { > { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, > { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, > { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, > + { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], }, > { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, > {}, > }; > > -- > 2.34.1
On Mon, Sep 23, 2024 at 02:59:22PM -0400, Frank Li wrote: Subject should specify 'i.MX8Q series of SoCs'. So it would become: 'PCI: imx6: Add PCIe Endpoint (EP) support for i.MX8Q series of SoCs' > Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe > Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the > CPU addresses. The DesignWare (DWC) driver already handles this in the > common code. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index bdc2b372e6c13..1e58c24137e7f 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -70,6 +70,7 @@ enum imx_pcie_variants { > IMX8MQ_EP, > IMX8MM_EP, > IMX8MP_EP, > + IMX8Q_EP, > IMX95_EP, > }; > > @@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { > .align = SZ_64K, > }; > > +static const struct pci_epc_features imx8q_pcie_epc_features = { > + .linkup_notifier = false, > + .msi_capable = true, > + .msix_capable = false, > + .bar[BAR_1] = { .type = BAR_RESERVED, }, > + .bar[BAR_3] = { .type = BAR_RESERVED, }, > + .bar[BAR_5] = { .type = BAR_RESERVED, }, > + .align = SZ_64K, > +}; > + > /* > * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme > * ================================================================================================ > @@ -1645,6 +1656,14 @@ static const struct imx_pcie_drvdata drvdata[] = { > .epc_features = &imx8m_pcie_epc_features, > .enable_ref_clk = imx8mm_pcie_enable_ref_clk, > }, > + [IMX8Q_EP] = { > + .variant = IMX8Q_EP, > + .flags = IMX_PCIE_FLAG_HAS_PHYDRV, > + .mode = DW_PCIE_EP_TYPE, > + .epc_features = &imx8q_pcie_epc_features, > + .clk_names = imx8q_clks, > + .clks_cnt = ARRAY_SIZE(imx8q_clks), > + }, > [IMX95_EP] = { > .variant = IMX95_EP, > .flags = IMX_PCIE_FLAG_HAS_SERDES | > @@ -1674,6 +1693,7 @@ static const struct of_device_id imx_pcie_of_match[] = { > { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, > { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, > { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, > + { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], }, > { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, > {}, > }; > > -- > 2.34.1 >
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index bdc2b372e6c13..1e58c24137e7f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -70,6 +70,7 @@ enum imx_pcie_variants { IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, + IMX8Q_EP, IMX95_EP, }; @@ -1079,6 +1080,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { .align = SZ_64K, }; +static const struct pci_epc_features imx8q_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, + .bar[BAR_1] = { .type = BAR_RESERVED, }, + .bar[BAR_3] = { .type = BAR_RESERVED, }, + .bar[BAR_5] = { .type = BAR_RESERVED, }, + .align = SZ_64K, +}; + /* * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme * ================================================================================================ @@ -1645,6 +1656,14 @@ static const struct imx_pcie_drvdata drvdata[] = { .epc_features = &imx8m_pcie_epc_features, .enable_ref_clk = imx8mm_pcie_enable_ref_clk, }, + [IMX8Q_EP] = { + .variant = IMX8Q_EP, + .flags = IMX_PCIE_FLAG_HAS_PHYDRV, + .mode = DW_PCIE_EP_TYPE, + .epc_features = &imx8q_pcie_epc_features, + .clk_names = imx8q_clks, + .clks_cnt = ARRAY_SIZE(imx8q_clks), + }, [IMX95_EP] = { .variant = IMX95_EP, .flags = IMX_PCIE_FLAG_HAS_SERDES | @@ -1674,6 +1693,7 @@ static const struct of_device_id imx_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, + { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], }, { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, {}, };
Add support for i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe Endpoint (EP). On i.MX8Q platforms, the PCI bus addresses differ from the CPU addresses. The DesignWare (DWC) driver already handles this in the common code. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)