[7/8] platform/chrome: cros_ec_typec: Thunderbolt support

Message ID	20240925092505.7.Ic61ced3cdfb5d6776435356061f12307da719829@changeid (mailing list archive)
State	New
Headers	show Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5F1613B2B6 for <chrome-platform@lists.linux.dev>; Wed, 25 Sep 2024 16:25:22 +0000 (UTC) From: Abhishek Pandit-Subedi <abhishekpandit@chromium.org> To: heikki.krogerus@linux.intel.com, tzungbi@kernel.org Cc: jthies@google.com, pmalani@chromium.org, akuchynski@google.com, Abhishek Pandit-Subedi <abhishekpandit@chromium.org>, Benson Leung <bleung@chromium.org>, Guenter Roeck <groeck@chromium.org>, chrome-platform@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] platform/chrome: cros_ec_typec: Thunderbolt support Date: Wed, 25 Sep 2024 09:25:08 -0700 Message-ID: <20240925092505.7.Ic61ced3cdfb5d6776435356061f12307da719829@changeid> In-Reply-To: <20240925162513.435177-1-abhishekpandit@chromium.org> References: <20240925162513.435177-1-abhishekpandit@chromium.org> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Thunderbolt and DP altmode support for cros-ec-typec \| expand [0/8] Thunderbolt and DP altmode support for cros-ec-typec [5/8] platform/chrome: cros_ec_typec: Update partner altmode active [6/8] platform/chrome: cros_ec_typec: Displayport support [7/8] platform/chrome: cros_ec_typec: Thunderbolt support [8/8] platform/chrome: cros_ec_typec: Disable auto_enter

diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index fe6c5234ac27..da7a44738171 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o cros-ec-typec-objs := cros_ec_typec.o cros_typec_vdm.o cros-ec-typec-$(CONFIG_TYPEC_DP_ALTMODE) += cros_typec_displayport.o +cros-ec-typec-$(CONFIG_TYPEC_TBT_ALTMODE) += cros_typec_thunderbolt.o obj-$(CONFIG_CROS_EC_TYPEC) += cros-ec-typec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index f9221d0d95f5..ec13d84d11b8 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -304,21 +304,26 @@ static int cros_typec_register_port_altmodes(struct cros_typec_data *typec, typec_altmode_set_drvdata(amode, port); amode->ops = &port_amode_ops; #endif - /* * Register TBT compatibility alt mode. The EC will not enter the mode - * if it doesn't support it, so it's safe to register it unconditionally - * here for now. + * if it doesn't support it and it will not enter automatically by + * design so we can use the |ap_driven_altmode| feature to check if we + * should register it. */ - memset(&desc, 0, sizeof(desc)); - desc.svid = USB_TYPEC_TBT_SID; - desc.mode = TYPEC_ANY_MODE; - amode = typec_port_register_altmode(port->port, &desc); - if (IS_ERR(amode)) - return PTR_ERR(amode); - port->port_altmode[CROS_EC_ALTMODE_TBT] = amode; - typec_altmode_set_drvdata(amode, port); - amode->ops = &port_amode_ops; + if (typec->ap_driven_altmode) { + memset(&desc, 0, sizeof(desc)); + desc.svid = USB_TYPEC_TBT_SID; + desc.mode = TYPEC_ANY_MODE; + amode = cros_typec_register_thunderbolt(port, &desc); + if (IS_ERR(amode)) + return PTR_ERR(amode); + port->port_altmode[CROS_EC_ALTMODE_TBT] = amode; + +#if !IS_ENABLED(CONFIG_TYPEC_TBT_ALTMODE) + typec_altmode_set_drvdata(amode, port); + amode->ops = &port_amode_ops; +#endif + } port->state.alt = NULL; port->state.mode = TYPEC_STATE_USB; diff --git a/drivers/platform/chrome/cros_typec_altmode.h b/drivers/platform/chrome/cros_typec_altmode.h index a8b37a18c83a..24e766189211 100644 --- a/drivers/platform/chrome/cros_typec_altmode.h +++ b/drivers/platform/chrome/cros_typec_altmode.h @@ -31,4 +31,18 @@ int cros_typec_displayport_status_update(struct typec_altmode *altmode, return 0; } #endif + +#if IS_ENABLED(CONFIG_TYPEC_TBT_ALTMODE) +struct typec_altmode * +cros_typec_register_thunderbolt(struct cros_typec_port *port, + struct typec_altmode_desc *desc); +#else +struct typec_altmode * +cros_typec_register_thunderbolt(struct cros_typec_port *port, + struct typec_altmode_desc *desc) +{ + return typec_port_register_altmode(port->port, desc); +} +#endif + #endif /* __CROS_TYPEC_ALTMODE_H__ */ diff --git a/drivers/platform/chrome/cros_typec_thunderbolt.c b/drivers/platform/chrome/cros_typec_thunderbolt.c new file mode 100644 index 000000000000..b399237b773f --- /dev/null +++ b/drivers/platform/chrome/cros_typec_thunderbolt.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Alt-mode implementation for Thunderbolt on ChromeOS EC. + * + * Copyright 2024 Google LLC + * Author: Abhishek Pandit-Subedi <abhishekpandit@chromium.org> + */ +#include "cros_ec_typec.h" + +#include <linux/usb/typec_tbt.h> +#include <linux/usb/pd_vdo.h> + +#include "cros_typec_altmode.h" + +struct typec_tbt_data { + struct work_struct work; + + struct cros_typec_port *port; + struct typec_altmode *alt; + + u32 header; + u32 *vdo_data; + u8 vdo_size; +}; + +static void cros_typec_thunderbolt_work(struct work_struct *work) +{ + struct typec_tbt_data *data = + container_of(work, struct typec_tbt_data, work); + + if (typec_altmode_vdm(data->alt, data->header, data->vdo_data, + data->vdo_size)) + dev_err(&data->alt->dev, "VDM 0x%x failed", data->header); + + data->header = 0; + data->vdo_data = NULL; + data->vdo_size = 0; +} + +static int cros_typec_thunderbolt_enter(struct typec_altmode *alt, u32 *vdo) +{ + struct typec_tbt_data *data = typec_altmode_get_drvdata(alt); + struct ec_params_typec_control req = { + .port = data->port->port_num, + .command = TYPEC_CONTROL_COMMAND_ENTER_MODE, + .mode_to_enter = CROS_EC_ALTMODE_TBT, + }; + int svdm_version; + int ret; + + ret = cros_ec_cmd(data->port->typec_data->ec, 0, EC_CMD_TYPEC_CONTROL, + &req, sizeof(req), NULL, 0); + if (ret < 0) + return ret; + + svdm_version = typec_altmode_get_svdm_version(alt); + if (svdm_version < 0) + return svdm_version; + + data->header = VDO(USB_TYPEC_TBT_SID, 1, svdm_version, CMD_ENTER_MODE); + data->header |= VDO_OPOS(TYPEC_TBT_MODE); + data->header |= VDO_CMDT(CMDT_RSP_ACK); + + data->vdo_data = NULL; + data->vdo_size = 1; + + schedule_work(&data->work); + + return ret; +} + +static int cros_typec_thunderbolt_exit(struct typec_altmode *alt) +{ + struct typec_tbt_data *data = typec_altmode_get_drvdata(alt); + struct ec_params_typec_control req = { + .port = data->port->port_num, + .command = TYPEC_CONTROL_COMMAND_EXIT_MODES, + }; + int svdm_version; + int ret; + + ret = cros_ec_cmd(data->port->typec_data->ec, 0, EC_CMD_TYPEC_CONTROL, + &req, sizeof(req), NULL, 0); + + if (ret < 0) + return ret; + + svdm_version = typec_altmode_get_svdm_version(alt); + if (svdm_version < 0) + return svdm_version; + + data->header = VDO(USB_TYPEC_TBT_SID, 1, svdm_version, CMD_EXIT_MODE); + data->header |= VDO_OPOS(TYPEC_TBT_MODE); + data->header |= VDO_CMDT(CMDT_RSP_ACK); + + data->vdo_data = NULL; + data->vdo_size = 1; + + schedule_work(&data->work); + + return ret; +} + +static int cros_typec_thunderbolt_vdm(struct typec_altmode *alt, u32 header, + const u32 *data, int count) +{ + struct typec_tbt_data *tbt_data = typec_altmode_get_drvdata(alt); + + int cmd_type = PD_VDO_CMDT(header); + int cmd = PD_VDO_CMD(header); + int svdm_version; + + svdm_version = typec_altmode_get_svdm_version(alt); + if (svdm_version < 0) + return svdm_version; + + switch (cmd_type) { + case CMDT_INIT: + if (PD_VDO_SVDM_VER(header) < svdm_version) { + typec_partner_set_svdm_version(tbt_data->port->partner, + PD_VDO_SVDM_VER(header)); + svdm_version = PD_VDO_SVDM_VER(header); + } + + tbt_data->header = VDO(USB_TYPEC_TBT_SID, 1, svdm_version, cmd); + tbt_data->header |= VDO_OPOS(TYPEC_TBT_MODE); + + /* + * TODO - Just always reply to the VDMs that we are done. + */ + switch (cmd) { + case CMD_ENTER_MODE: + /* Don't respond to the enter mode vdm because it + * triggers mux configuration. This is handled directly + * by the cros_ec_typec driver so the Thunderbolt driver + * doesn't need to be involved. + */ + break; + default: + tbt_data->header |= VDO_CMDT(CMDT_RSP_ACK); + schedule_work(&tbt_data->work); + break; + } + + break; + default: + break; + } + + return 0; +} + +static const struct typec_altmode_ops cros_typec_thunderbolt_ops = { + .enter = cros_typec_thunderbolt_enter, + .exit = cros_typec_thunderbolt_exit, + .vdm = cros_typec_thunderbolt_vdm, +}; + +struct typec_altmode * +cros_typec_register_thunderbolt(struct cros_typec_port *port, + struct typec_altmode_desc *desc) +{ + struct typec_altmode *alt; + struct typec_tbt_data *data; + + alt = typec_port_register_altmode(port->port, desc); + if (IS_ERR(alt)) + return alt; + + data = devm_kzalloc(&alt->dev, sizeof(*data), GFP_KERNEL); + if (!data) { + typec_unregister_altmode(alt); + return ERR_PTR(-ENOMEM); + } + + INIT_WORK(&data->work, cros_typec_thunderbolt_work); + data->alt = alt; + data->port = port; + + typec_altmode_set_ops(alt, &cros_typec_thunderbolt_ops); + typec_altmode_set_drvdata(alt, data); + + return alt; +}

[7/8] platform/chrome: cros_ec_typec: Thunderbolt support

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