| Message ID | 20240926-preemption-a750-t-v6-4-7b6e1ef3648f@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Preemption support for A7XX | expand |
In the future, the right thing to do is open a mesa MR with just the register changes and then copy the file from mesa once it's merged, because all of the XML files are supposed to flow from mesa to keep mesa and the kernel in sync. I've opened a mesa MR [1] based on this that will hopefully get quickly acked and merged. Connor [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31422 On Thu, Sep 26, 2024 at 10:17 PM Antonino Maniscalco <antomani103@gmail.com> wrote: > > Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml. > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK > Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> > --- > drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml > index 2dfe6913ab4f52449b76c2f75b2d101c08115d16..fd31d1d7a11eef7f38dcc2975dc1034f6b7a2e41 100644 > --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml > +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml > @@ -1337,7 +1337,12 @@ to upconvert to 32b float internally? > <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> > </array> > > - <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/> > + <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"> > + <bitfield name="STOP" pos="0" type="boolean"/> This bit isn't set to 1 when it's stopped, it's set to > + <bitfield name="LEVEL" low="6" high="7"/> > + <bitfield name="USES_GMEM" pos="8" type="boolean"/> > + <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/> > + </reg32> > <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> > <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> > <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/> > > -- > 2.46.1 >
On 9/27/24 1:57 PM, Connor Abbott wrote: > In the future, the right thing to do is open a mesa MR with just the > register changes and then copy the file from mesa once it's merged, > because all of the XML files are supposed to flow from mesa to keep > mesa and the kernel in sync. I've opened a mesa MR [1] based on this > that will hopefully get quickly acked and merged. > > Connor Sure I'll keep that in mind, thanks! > > [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31422 > > On Thu, Sep 26, 2024 at 10:17 PM Antonino Maniscalco > <antomani103@gmail.com> wrote: >> >> Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml. >> >> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD >> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD >> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK >> Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> >> --- >> drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml >> index 2dfe6913ab4f52449b76c2f75b2d101c08115d16..fd31d1d7a11eef7f38dcc2975dc1034f6b7a2e41 100644 >> --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml >> +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml >> @@ -1337,7 +1337,12 @@ to upconvert to 32b float internally? >> <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> >> </array> >> >> - <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/> >> + <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"> >> + <bitfield name="STOP" pos="0" type="boolean"/> > > This bit isn't set to 1 when it's stopped, it's set to > >> + <bitfield name="LEVEL" low="6" high="7"/> >> + <bitfield name="USES_GMEM" pos="8" type="boolean"/> >> + <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/> >> + </reg32> >> <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> >> <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> >> <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/> >> >> -- >> 2.46.1 >> Best regards,
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 2dfe6913ab4f52449b76c2f75b2d101c08115d16..fd31d1d7a11eef7f38dcc2975dc1034f6b7a2e41 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -1337,7 +1337,12 @@ to upconvert to 32b float internally? <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> </array> - <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/> + <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"> + <bitfield name="STOP" pos="0" type="boolean"/> + <bitfield name="LEVEL" low="6" high="7"/> + <bitfield name="USES_GMEM" pos="8" type="boolean"/> + <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/> + </reg32> <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>