| Message ID | fe72fb72acde4f5d9f8bd1a012435519592bd2bc.1727441772.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 6695b5500ba4b83aaabf4eb2434f71ce1910f28c |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | ARM: dts: renesas: rskrza1: Enable watchdog timer | expand |
On Fri, Sep 27, 2024 at 02:57:37PM +0200, Geert Uytterhoeven wrote: > Enable the Watchdog Timer (WDT) on the Renesas RSK+RZA1 development > board equipped with an RZ/A1H SoC. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts index 43990911b144dde9..6f7fa3eeeb79893f 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts @@ -285,3 +285,8 @@ &scif2 { pinctrl-0 = <&scif2_pins>; status = "okay"; }; + +&wdt { + timeout-sec = <60>; + status = "okay"; +};
Enable the Watchdog Timer (WDT) on the Renesas RSK+RZA1 development board equipped with an RZ/A1H SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- To be queued in renesas-devel for v6.13. arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts | 5 +++++ 1 file changed, 5 insertions(+)