| Message ID | 20240927141445.157234-2-iansdannapel@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver | expand |
On 27/09/2024 16:14, iansdannapel@gmail.com wrote: > From: Ian Dannapel <iansdannapel@gmail.com> > > Add device tree binding documentation for configuring Efinix FPGA > using serial SPI passive programming mode. > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > --- > .../fpga/efinix,trion-spi-passive.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > > diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > new file mode 100644 > index 000000000000..ec6697fa6f44 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Efinix SPI FPGA Manager > + > +maintainers: > + - Ian Dannapel <iansdannapel@gmail.com> > + > +description: | > + Efinix Trion and Titanium Series FPGAs support a method of loading the > + bitstream over what is referred to as "SPI Passive Programming". > + Only serial (1x bus width) is supported, setting the programming mode > + is not in the scope the this manager and must be done elsewhere. > + > + Warning: The slave serial link is not technically SPI and therefore it is > + not recommended to have other devices on the same bus since it might > + interfere or be interfered by other transmissions. > + > + References: > + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf > + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf > + > +allOf: > + - $ref: /schemas/spi/spi-peripheral-props.yaml# > + > +properties: > + compatible: > + enum: > + - efinix,trion-spi-passive > + - efinix,titanium-spi-passive 1. Your driver suggests these are compatible, so make them compatible with using fallback. 2. What is "spi-passive"? Compatible is supposed to be the name of the device, so I assume this is "trion"? Can trion be anything else than fpga? > + > + spi-cpha: true > + > + spi-cpol: true > + > + spi-max-frequency: > + maximum: 25000000 > + > + reg: > + maxItems: 1 > + > + creset-gpios: reset-gpios Do not invent own properties. > + description: > + reset and re-configuration trigger pin (low active) > + maxItems: 1 > + > + cs-gpios: > + description: > + chip-select pin (low active) Eee? That's a property of controller, not child. Aren't you duplicating existing controller property? > + maxItems: 1 > + > + cdone-gpios: > + description: > + optional configuration done status pin (high active) > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - creset-gpios > + - cs-gpios > + > +additionalProperties: false unevaluatedProperties instead > + Best regards, Krzysztof
Thanks for the review Krzysztof. Am Fr., 27. Sept. 2024 um 16:26 Uhr schrieb Krzysztof Kozlowski <krzk@kernel.org>: > > On 27/09/2024 16:14, iansdannapel@gmail.com wrote: > > From: Ian Dannapel <iansdannapel@gmail.com> > > > > Add device tree binding documentation for configuring Efinix FPGA > > using serial SPI passive programming mode. > > > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > > --- > > .../fpga/efinix,trion-spi-passive.yaml | 85 +++++++++++++++++++ > > 1 file changed, 85 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > > > > diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > > new file mode 100644 > > index 000000000000..ec6697fa6f44 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > > @@ -0,0 +1,85 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Efinix SPI FPGA Manager > > + > > +maintainers: > > + - Ian Dannapel <iansdannapel@gmail.com> > > + > > +description: | > > + Efinix Trion and Titanium Series FPGAs support a method of loading the > > + bitstream over what is referred to as "SPI Passive Programming". > > + Only serial (1x bus width) is supported, setting the programming mode > > + is not in the scope the this manager and must be done elsewhere. > > + > > + Warning: The slave serial link is not technically SPI and therefore it is > > + not recommended to have other devices on the same bus since it might > > + interfere or be interfered by other transmissions. > > + > > + References: > > + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf > > + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf > > + > > +allOf: > > + - $ref: /schemas/spi/spi-peripheral-props.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - efinix,trion-spi-passive > > + - efinix,titanium-spi-passive > > 1. Your driver suggests these are compatible, so make them compatible > with using fallback. > > 2. What is "spi-passive"? Compatible is supposed to be the name of the > device, so I assume this is "trion"? Can trion be anything else than fpga? spi-passive is the programming mode, where the device is in slave mode. There are also other modes, but not supported by this driver. The name was inspired by similar drivers (spi-xilinx.c). Isn't just "efinix,trion"/"efinix,titanium" too generic? > > > + > > + spi-cpha: true > > + > > + spi-cpol: true > > + > > + spi-max-frequency: > > + maximum: 25000000 > > + > > + reg: > > + maxItems: 1 > > + > > + creset-gpios: > > reset-gpios > > Do not invent own properties. > > > + description: > > + reset and re-configuration trigger pin (low active) > > + maxItems: 1 > > + > > + cs-gpios: > > + description: > > + chip-select pin (low active) > > Eee? That's a property of controller, not child. Aren't you duplicating > existing controller property? This device uses this pin in combination with the reset to enter the programming mode. Also, the driver must guarantee that the pin is active for the whole transfer process, including ending dummy bits. This is why I added a warning to NOT use this driver with other devices on the same bus. > > > + maxItems: 1 > > + > > + cdone-gpios: > > + description: > > + optional configuration done status pin (high active) > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - creset-gpios > > + - cs-gpios > > + > > +additionalProperties: false > > unevaluatedProperties instead > > > + > > > > Best regards, > Krzysztof > Best regards, Ian
On 27/09/2024 17:34, Ian Dannapel wrote: > Thanks for the review Krzysztof. > > Am Fr., 27. Sept. 2024 um 16:26 Uhr schrieb Krzysztof Kozlowski > <krzk@kernel.org>: >> >> On 27/09/2024 16:14, iansdannapel@gmail.com wrote: >>> From: Ian Dannapel <iansdannapel@gmail.com> >>> >>> Add device tree binding documentation for configuring Efinix FPGA >>> using serial SPI passive programming mode. >>> >>> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> >>> --- >>> .../fpga/efinix,trion-spi-passive.yaml | 85 +++++++++++++++++++ >>> 1 file changed, 85 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml >>> new file mode 100644 >>> index 000000000000..ec6697fa6f44 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml >>> @@ -0,0 +1,85 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Efinix SPI FPGA Manager >>> + >>> +maintainers: >>> + - Ian Dannapel <iansdannapel@gmail.com> >>> + >>> +description: | >>> + Efinix Trion and Titanium Series FPGAs support a method of loading the >>> + bitstream over what is referred to as "SPI Passive Programming". >>> + Only serial (1x bus width) is supported, setting the programming mode >>> + is not in the scope the this manager and must be done elsewhere. >>> + >>> + Warning: The slave serial link is not technically SPI and therefore it is >>> + not recommended to have other devices on the same bus since it might >>> + interfere or be interfered by other transmissions. >>> + >>> + References: >>> + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf >>> + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf >>> + >>> +allOf: >>> + - $ref: /schemas/spi/spi-peripheral-props.yaml# >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - efinix,trion-spi-passive >>> + - efinix,titanium-spi-passive >> >> 1. Your driver suggests these are compatible, so make them compatible >> with using fallback. >> >> 2. What is "spi-passive"? Compatible is supposed to be the name of the >> device, so I assume this is "trion"? Can trion be anything else than fpga? > spi-passive is the programming mode, where the device is in slave > mode. There are also other modes, but not supported by this driver. But we do no describe here drivers, so it does no matter what it supports. > The name was inspired by similar drivers (spi-xilinx.c). Isn't just > "efinix,trion"/"efinix,titanium" too generic? What do you mean too generic? What else could it be? BTW, that was my question, which you did not answer. Bindings describe hardware, so describe here hardware. >> >>> + >>> + spi-cpha: true >>> + >>> + spi-cpol: true >>> + >>> + spi-max-frequency: >>> + maximum: 25000000 >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + creset-gpios: >> >> reset-gpios >> >> Do not invent own properties. >> >>> + description: >>> + reset and re-configuration trigger pin (low active) >>> + maxItems: 1 >>> + >>> + cs-gpios: >>> + description: >>> + chip-select pin (low active) >> >> Eee? That's a property of controller, not child. Aren't you duplicating >> existing controller property? > This device uses this pin in combination with the reset to enter the > programming mode. Also, the driver must guarantee that the pin is Isn't this the same on every SPI device? > active for the whole transfer process, including ending dummy bits. > This is why I added a warning to NOT use this driver with other > devices on the same bus. Not really related. None of this grants exception from duplicating controller's property. How do you think it will even work in Linux, if same GPIO is requested twice (imagine controller also has it)? Till now, this would be -EBUSY. But regardless of implementation, I still do not understand why do you need duplicate same chip-select. Maybe just the naming is the confusion, dunno. Best regards, Krzysztof
Am Sa., 28. Sept. 2024 um 09:31 Uhr schrieb Krzysztof Kozlowski <krzk@kernel.org>: > > On 27/09/2024 17:34, Ian Dannapel wrote: > > Thanks for the review Krzysztof. > > > > Am Fr., 27. Sept. 2024 um 16:26 Uhr schrieb Krzysztof Kozlowski > > <krzk@kernel.org>: > >> > >> On 27/09/2024 16:14, iansdannapel@gmail.com wrote: > >>> From: Ian Dannapel <iansdannapel@gmail.com> > >>> > >>> Add device tree binding documentation for configuring Efinix FPGA > >>> using serial SPI passive programming mode. > >>> > >>> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > >>> --- > >>> .../fpga/efinix,trion-spi-passive.yaml | 85 +++++++++++++++++++ > >>> 1 file changed, 85 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > >>> new file mode 100644 > >>> index 000000000000..ec6697fa6f44 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml > >>> @@ -0,0 +1,85 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: Efinix SPI FPGA Manager > >>> + > >>> +maintainers: > >>> + - Ian Dannapel <iansdannapel@gmail.com> > >>> + > >>> +description: | > >>> + Efinix Trion and Titanium Series FPGAs support a method of loading the > >>> + bitstream over what is referred to as "SPI Passive Programming". > >>> + Only serial (1x bus width) is supported, setting the programming mode > >>> + is not in the scope the this manager and must be done elsewhere. > >>> + > >>> + Warning: The slave serial link is not technically SPI and therefore it is > >>> + not recommended to have other devices on the same bus since it might > >>> + interfere or be interfered by other transmissions. > >>> + > >>> + References: > >>> + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf > >>> + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf > >>> + > >>> +allOf: > >>> + - $ref: /schemas/spi/spi-peripheral-props.yaml# > >>> + > >>> +properties: > >>> + compatible: > >>> + enum: > >>> + - efinix,trion-spi-passive > >>> + - efinix,titanium-spi-passive > >> > >> 1. Your driver suggests these are compatible, so make them compatible > >> with using fallback. > >> > >> 2. What is "spi-passive"? Compatible is supposed to be the name of the > >> device, so I assume this is "trion"? Can trion be anything else than fpga? > > spi-passive is the programming mode, where the device is in slave > > mode. There are also other modes, but not supported by this driver. > > But we do no describe here drivers, so it does no matter what it supports. > > > The name was inspired by similar drivers (spi-xilinx.c). Isn't just > > "efinix,trion"/"efinix,titanium" too generic? > > What do you mean too generic? What else could it be? BTW, that was my > question, which you did not answer. Bindings describe hardware, so > describe here hardware. > > >> > >>> + > >>> + spi-cpha: true > >>> + > >>> + spi-cpol: true > >>> + > >>> + spi-max-frequency: > >>> + maximum: 25000000 > >>> + > >>> + reg: > >>> + maxItems: 1 > >>> + > >>> + creset-gpios: > >> > >> reset-gpios > >> > >> Do not invent own properties. > >> > >>> + description: > >>> + reset and re-configuration trigger pin (low active) > >>> + maxItems: 1 > >>> + > >>> + cs-gpios: > >>> + description: > >>> + chip-select pin (low active) > >> > >> Eee? That's a property of controller, not child. Aren't you duplicating > >> existing controller property? > > This device uses this pin in combination with the reset to enter the > > programming mode. Also, the driver must guarantee that the pin is > > Isn't this the same on every SPI device? Yes, but I was not very clear. In this case the pin must be hold active including entering the programming mode. And if the controller transfers the data in bursts, the pin is also not allowed to go inactive between transfer bursts. > > > active for the whole transfer process, including ending dummy bits. > > This is why I added a warning to NOT use this driver with other > > devices on the same bus. > > Not really related. None of this grants exception from duplicating > controller's property. > > How do you think it will even work in Linux, if same GPIO is requested > twice (imagine controller also has it)? Till now, this would be -EBUSY. I expected that the controller is not able request the same gpio. From the controller point of view, it is a device that does not have a chip select. Not sure if the controller would be able to get to this gpio if it is not explicitly given. > > But regardless of implementation, I still do not understand why do you > need duplicate same chip-select. Maybe just the naming is the confusion, > dunno. This could be an option to make the difference to a "real chip-select" clear, but it would drift away from the datasheet naming. Eg, prog-select? > > > Best regards, > Krzysztof > Regards, Ian
On 28/09/2024 14:33, Ian Dannapel wrote: >>>> >>>>> + >>>>> + spi-cpha: true >>>>> + >>>>> + spi-cpol: true >>>>> + >>>>> + spi-max-frequency: >>>>> + maximum: 25000000 >>>>> + >>>>> + reg: >>>>> + maxItems: 1 >>>>> + >>>>> + creset-gpios: >>>> >>>> reset-gpios >>>> >>>> Do not invent own properties. >>>> >>>>> + description: >>>>> + reset and re-configuration trigger pin (low active) >>>>> + maxItems: 1 >>>>> + >>>>> + cs-gpios: >>>>> + description: >>>>> + chip-select pin (low active) >>>> >>>> Eee? That's a property of controller, not child. Aren't you duplicating >>>> existing controller property? >>> This device uses this pin in combination with the reset to enter the >>> programming mode. Also, the driver must guarantee that the pin is >> >> Isn't this the same on every SPI device? > Yes, but I was not very clear. In this case the pin must be hold > active including entering the programming mode. And if the controller Just like every CS, no? The only difference is that you must send entire programming sequence without releasing the CS. > transfers the data in bursts, the pin is also not allowed to go > inactive between transfer bursts. >> >>> active for the whole transfer process, including ending dummy bits. >>> This is why I added a warning to NOT use this driver with other >>> devices on the same bus. >> >> Not really related. None of this grants exception from duplicating >> controller's property. >> >> How do you think it will even work in Linux, if same GPIO is requested >> twice (imagine controller also has it)? Till now, this would be -EBUSY. > I expected that the controller is not able request the same gpio. From > the controller point of view, it is a device that does not have a chip > select. Not sure if the controller would be able to get to this gpio > if it is not explicitly given. But it could be given. Don't think only about your case. Your description earlier clearly suggests it is CS. Description here suggests it is not a CS. No clue then. >> >> But regardless of implementation, I still do not understand why do you >> need duplicate same chip-select. Maybe just the naming is the confusion, >> dunno. > This could be an option to make the difference to a "real chip-select" > clear, but it would drift away from the datasheet naming. Eg, > prog-select? Please go back to datasheet. Which pin is this? CS, yes or not? If not, then which other pin is CS? Best regards, Krzysztof
Am Sa., 28. Sept. 2024 um 14:53 Uhr schrieb Krzysztof Kozlowski <krzk@kernel.org>: > > On 28/09/2024 14:33, Ian Dannapel wrote: > >>>> > >>>>> + > >>>>> + spi-cpha: true > >>>>> + > >>>>> + spi-cpol: true > >>>>> + > >>>>> + spi-max-frequency: > >>>>> + maximum: 25000000 > >>>>> + > >>>>> + reg: > >>>>> + maxItems: 1 > >>>>> + > >>>>> + creset-gpios: > >>>> > >>>> reset-gpios > >>>> > >>>> Do not invent own properties. > >>>> > >>>>> + description: > >>>>> + reset and re-configuration trigger pin (low active) > >>>>> + maxItems: 1 > >>>>> + > >>>>> + cs-gpios: > >>>>> + description: > >>>>> + chip-select pin (low active) > >>>> > >>>> Eee? That's a property of controller, not child. Aren't you duplicating > >>>> existing controller property? > >>> This device uses this pin in combination with the reset to enter the > >>> programming mode. Also, the driver must guarantee that the pin is > >> > >> Isn't this the same on every SPI device? > > Yes, but I was not very clear. In this case the pin must be hold > > active including entering the programming mode. And if the controller > > Just like every CS, no? > > The only difference is that you must send entire programming sequence > without releasing the CS. > > > transfers the data in bursts, the pin is also not allowed to go > > inactive between transfer bursts. > >> > >>> active for the whole transfer process, including ending dummy bits. > >>> This is why I added a warning to NOT use this driver with other > >>> devices on the same bus. > >> > >> Not really related. None of this grants exception from duplicating > >> controller's property. > >> > >> How do you think it will even work in Linux, if same GPIO is requested > >> twice (imagine controller also has it)? Till now, this would be -EBUSY. > > I expected that the controller is not able request the same gpio. From > > the controller point of view, it is a device that does not have a chip > > select. Not sure if the controller would be able to get to this gpio > > if it is not explicitly given. > > But it could be given. Don't think only about your case. it won't work if the controller also may request this gpio or interfere with it. > > Your description earlier clearly suggests it is CS. Description here > suggests it is not a CS. > > No clue then. > > >> > >> But regardless of implementation, I still do not understand why do you > >> need duplicate same chip-select. Maybe just the naming is the confusion, > >> dunno. > > This could be an option to make the difference to a "real chip-select" > > clear, but it would drift away from the datasheet naming. Eg, > > prog-select? > > Please go back to datasheet. Which pin is this? CS, yes or not? If not, > then which other pin is CS? Yes, this pin in question is referred to as the Chip Select (CS) or Slave Select in the datasheet and pinout. It is used in combination with the reset for entering the programming mode and then used for the SPI data transfer to the FPGA’s volatile configuration RAM. There must be no state change on this CS pin between entering programming mode and the completion of the SPI transfer. Since the controller chip-select functionality can't fulfill these requirements for this device, the proposed solution is to move this pin from the controller to the child driver. > > Best regards, > Krzysztof > Best regards Ian
On Sat, Sep 28, 2024 at 04:26:03PM +0200, Ian Dannapel wrote: > Am Sa., 28. Sept. 2024 um 14:53 Uhr schrieb Krzysztof Kozlowski > <krzk@kernel.org>: > > > > On 28/09/2024 14:33, Ian Dannapel wrote: > > >>>> > > >>>>> + > > >>>>> + spi-cpha: true > > >>>>> + > > >>>>> + spi-cpol: true > > >>>>> + > > >>>>> + spi-max-frequency: > > >>>>> + maximum: 25000000 > > >>>>> + > > >>>>> + reg: > > >>>>> + maxItems: 1 > > >>>>> + > > >>>>> + creset-gpios: > > >>>> > > >>>> reset-gpios > > >>>> > > >>>> Do not invent own properties. > > >>>> > > >>>>> + description: > > >>>>> + reset and re-configuration trigger pin (low active) > > >>>>> + maxItems: 1 > > >>>>> + > > >>>>> + cs-gpios: > > >>>>> + description: > > >>>>> + chip-select pin (low active) > > >>>> > > >>>> Eee? That's a property of controller, not child. Aren't you duplicating > > >>>> existing controller property? > > >>> This device uses this pin in combination with the reset to enter the > > >>> programming mode. Also, the driver must guarantee that the pin is > > >> > > >> Isn't this the same on every SPI device? > > > Yes, but I was not very clear. In this case the pin must be hold > > > active including entering the programming mode. And if the controller > > > > Just like every CS, no? > > > > The only difference is that you must send entire programming sequence > > without releasing the CS. > > > > > transfers the data in bursts, the pin is also not allowed to go > > > inactive between transfer bursts. > > >> > > >>> active for the whole transfer process, including ending dummy bits. > > >>> This is why I added a warning to NOT use this driver with other > > >>> devices on the same bus. > > >> > > >> Not really related. None of this grants exception from duplicating > > >> controller's property. > > >> > > >> How do you think it will even work in Linux, if same GPIO is requested > > >> twice (imagine controller also has it)? Till now, this would be -EBUSY. > > > I expected that the controller is not able request the same gpio. From > > > the controller point of view, it is a device that does not have a chip > > > select. Not sure if the controller would be able to get to this gpio > > > if it is not explicitly given. > > > > But it could be given. Don't think only about your case. > it won't work if the controller also may request this gpio or interfere with it. Then your binding is incomplete, I would say. What stops anyone from providing the same GPIO for CS in controller node, like typical bindings expect? > > > > Your description earlier clearly suggests it is CS. Description here > > suggests it is not a CS. > > > > No clue then. > > > > >> > > >> But regardless of implementation, I still do not understand why do you > > >> need duplicate same chip-select. Maybe just the naming is the confusion, > > >> dunno. > > > This could be an option to make the difference to a "real chip-select" > > > clear, but it would drift away from the datasheet naming. Eg, > > > prog-select? > > > > Please go back to datasheet. Which pin is this? CS, yes or not? If not, > > then which other pin is CS? > Yes, this pin in question is referred to as the Chip Select (CS) or > Slave Select in the datasheet and pinout. > It is used in combination with the reset for entering the programming > mode and then used for the SPI data transfer to the FPGA’s volatile > configuration RAM. > There must be no state change on this CS pin between entering > programming mode and the completion of the SPI transfer. You just described CS gpio in parent controller node. > Since the controller chip-select functionality can't fulfill these > requirements for this device, the proposed solution is to move this > pin from the controller to the child driver. You mix two different things. Where the property should be described and how it should be handled. child driver is not the matter of bindings. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml new file mode 100644 index 000000000000..ec6697fa6f44 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel <iansdannapel@gmail.com> + +description: | + Efinix Trion and Titanium Series FPGAs support a method of loading the + bitstream over what is referred to as "SPI Passive Programming". + Only serial (1x bus width) is supported, setting the programming mode + is not in the scope the this manager and must be done elsewhere. + + Warning: The slave serial link is not technically SPI and therefore it is + not recommended to have other devices on the same bus since it might + interfere or be interfered by other transmissions. + + References: + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - efinix,trion-spi-passive + - efinix,titanium-spi-passive + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + creset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cs-gpios: + description: + chip-select pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - creset-gpios + - cs-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + fpga-mgr@0 { + compatible = "efinix,trion-spi-passive"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + creset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +...