| Message ID | 20240908125920.1160236-7-zhao1.liu@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce SMP Cache Topology | expand |
Hi Ali, [snip] > > + > > + /* > > + * TODO: Add a SMPCompatProps.has_caches flag to avoid useless > > Updates > > + * if user didn't set smp_cache. > > + */ > Hi Zhao, > > Thanks for sending this patchset so quickly. I really appreciate the > TODO already :) Welcome! And I'm also sorry for a long silence. Now I'm back from the vacation and will keep pushing this series forward. > It also helps me avoid going through every single > layer, especially when I want to avoid matching system registers in > ARM, particularly when there's no description in the command line. Great! I also noticed your patch for this "TODO" and will help you review it soon. Regards, Zhao > > + x86_cpu_update_smp_cache_topo(ms, cpu); > > + > > qemu_register_reset(x86_cpu_machine_reset_cb, cpu); > > > > if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > > > 1) { >
On Tue, Sep 17, 2024 at 10:06:41AM +0100, Jonathan Cameron wrote: > Date: Tue, 17 Sep 2024 10:06:41 +0100 > From: Jonathan Cameron <Jonathan.Cameron@Huawei.com> > Subject: Re: [PATCH v2 6/7] i386/cpu: Update cache topology with machine's > configuration > X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) > > On Sun, 8 Sep 2024 20:59:19 +0800 > Zhao Liu <zhao1.liu@intel.com> wrote: > > > User will configure smp cache topology via -machine smp-cache. > > > > For this case, update the x86 CPUs' cache topology with user's > > configuration in MachineState. > > > > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > > Tested-by: Yongwei Ma <yongwei.ma@intel.com> > Seems simple enough. > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Thanks! -Zhao
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e9f755000356..6d9f7dc0872a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7597,6 +7597,38 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_limits[2] = 0; } +#ifndef CONFIG_USER_ONLY +static void x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + CpuTopologyLevel level; + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1d_cache->share_level = level; + env->cache_info_amd.l1d_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1i_cache->share_level = level; + env->cache_info_amd.l1i_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l2_cache->share_level = level; + env->cache_info_amd.l2_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); + if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l3_cache->share_level = level; + env->cache_info_amd.l3_cache->share_level = level; + } +} +#endif + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -7821,6 +7853,13 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + + /* + * TODO: Add a SMPCompatProps.has_caches flag to avoid useless Updates + * if user didn't set smp_cache. + */ + x86_cpu_update_smp_cache_topo(ms, cpu); + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {