| Message ID | 20241006-fix-sm8450-pcie1-v1-1-4f227c9082ed@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 5d3d966400d0a094359009147d742b3926a2ea53 |
| Headers | show |
| Series | arm64: dts: qcom: sm8450 fix PIPE clock specification for pcie1 | expand |
On 6.10.2024 6:47 PM, Dmitry Baryshkov wrote: > For historical reasons on SM8450 the second PCIe host (pcie1) also keeps > a reference to the PIPE clock coming from the PHY. Commit e76862840660 > ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") has > updated the PHY to use #clock-cells = <1>, making just <&pcie1_phy> > clock specification invalid. Update corresponding clock entry in the > PCIe1 host node. > > /soc@0/pcie@1c08000: Failed to get clk index: 2 ret: -22 > qcom-pcie 1c08000.pcie: Failed to get clocks > qcom-pcie 1c08000.pcie: probe with driver qcom-pcie failed with error -22 > > Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
On 06/10/2024 18:47, Dmitry Baryshkov wrote: > For historical reasons on SM8450 the second PCIe host (pcie1) also keeps > a reference to the PIPE clock coming from the PHY. Commit e76862840660 > ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") has > updated the PHY to use #clock-cells = <1>, making just <&pcie1_phy> > clock specification invalid. Update corresponding clock entry in the > PCIe1 host node. > > /soc@0/pcie@1c08000: Failed to get clk index: 2 ret: -22 > qcom-pcie 1c08000.pcie: Failed to get clocks > qcom-pcie 1c08000.pcie: probe with driver qcom-pcie failed with error -22 > > Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 9bafb3b350ff..38cb524cc568 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -1973,7 +1973,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, > <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, > - <&pcie1_phy>, > + <&pcie1_phy QMP_PCIE_PIPE_CLK>, > <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_PCIE_1_AUX_CLK>, > <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > > --- > base-commit: 58ca61c1a866bfdaa5e19fb19a2416764f847d75 > change-id: 20241006-fix-sm8450-pcie1-4be23e8bf156 > > Best regards, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On Sun, 06 Oct 2024 19:47:56 +0300, Dmitry Baryshkov wrote: > For historical reasons on SM8450 the second PCIe host (pcie1) also keeps > a reference to the PIPE clock coming from the PHY. Commit e76862840660 > ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") has > updated the PHY to use #clock-cells = <1>, making just <&pcie1_phy> > clock specification invalid. Update corresponding clock entry in the > PCIe1 host node. > > [...] Applied, thanks! [1/1] arm64: dts: qcom: sm8450 fix PIPE clock specification for pcie1 commit: 5d3d966400d0a094359009147d742b3926a2ea53 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9bafb3b350ff..38cb524cc568 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1973,7 +1973,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_phy>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
For historical reasons on SM8450 the second PCIe host (pcie1) also keeps a reference to the PIPE clock coming from the PHY. Commit e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") has updated the PHY to use #clock-cells = <1>, making just <&pcie1_phy> clock specification invalid. Update corresponding clock entry in the PCIe1 host node. /soc@0/pcie@1c08000: Failed to get clk index: 2 ret: -22 qcom-pcie 1c08000.pcie: Failed to get clocks qcom-pcie 1c08000.pcie: probe with driver qcom-pcie failed with error -22 Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- base-commit: 58ca61c1a866bfdaa5e19fb19a2416764f847d75 change-id: 20241006-fix-sm8450-pcie1-4be23e8bf156 Best regards,