| Message ID | 20241008223741.82790-8-matthew.s.atwood@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add xe3lpd edp enabling | expand |
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> -Clint On Tue, 2024-10-08 at 15:37 -0700, Matt Atwood wrote: > From: Suraj Kandpal <suraj.kandpal@intel.com> > > From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of > DP and eDP been merged and now use the same rates and values. eDP > over TypeC has also been introduced. > Moreover it allows more granular and higher rates. Add new table to > represent this change. > > Bspec: 68961 > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 24 ++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 4a6c3040ca15..0d6f75ae35f5 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -1122,6 +1122,22 @@ static const struct intel_c20pll_state * const > xe2hpd_c20_dp_tables[] = { > NULL, > }; > > +static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = { > + &mtl_c20_dp_rbr, > + &xe2hpd_c20_edp_r216, > + &xe2hpd_c20_edp_r243, > + &mtl_c20_dp_hbr1, > + &xe2hpd_c20_edp_r324, > + &xe2hpd_c20_edp_r432, > + &mtl_c20_dp_hbr2, > + &xe2hpd_c20_edp_r675, > + &mtl_c20_dp_hbr3, > + &mtl_c20_dp_uhbr10, > + &xe2hpd_c20_dp_uhbr13_5, > + &mtl_c20_dp_uhbr20, > + NULL, > +}; > + > /* > * HDMI link rates with 38.4 MHz reference clock. > */ > @@ -2242,11 +2258,15 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > if (intel_crtc_has_dp_encoder(crtc_state)) { > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > - return xe2hpd_c20_edp_tables; > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { > + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) > + return xe2hpd_c20_edp_tables; > + } > > if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) > return xe2hpd_c20_dp_tables; > + else if (DISPLAY_VER(i915) >= 30) > + return xe3lpd_c20_dp_edp_tables; > else > return mtl_c20_dp_tables; >
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 4a6c3040ca15..0d6f75ae35f5 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -1122,6 +1122,22 @@ static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = { NULL, }; +static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = { + &mtl_c20_dp_rbr, + &xe2hpd_c20_edp_r216, + &xe2hpd_c20_edp_r243, + &mtl_c20_dp_hbr1, + &xe2hpd_c20_edp_r324, + &xe2hpd_c20_edp_r432, + &mtl_c20_dp_hbr2, + &xe2hpd_c20_edp_r675, + &mtl_c20_dp_hbr3, + &mtl_c20_dp_uhbr10, + &xe2hpd_c20_dp_uhbr13_5, + &mtl_c20_dp_uhbr20, + NULL, +}; + /* * HDMI link rates with 38.4 MHz reference clock. */ @@ -2242,11 +2258,15 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_dp_encoder(crtc_state)) { - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - return xe2hpd_c20_edp_tables; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) + return xe2hpd_c20_edp_tables; + } if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) return xe2hpd_c20_dp_tables; + else if (DISPLAY_VER(i915) >= 30) + return xe3lpd_c20_dp_edp_tables; else return mtl_c20_dp_tables;