| Message ID | 20240531202813.277109-1-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: lcdif: Use adjusted_mode .clock instead of .crtc_clock | expand |
Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek Vasut: > In case an upstream bridge modified the required clock frequency > in its .atomic_check callback by setting adjusted_mode.clock , > make sure that clock frequency is generated by the LCDIFv3 block. > > This is useful e.g. when LCDIFv3 feeds DSIM which feeds TC358767 > with (e)DP output, where the TC358767 expects precise timing on > its input side, the precise timing must be generated by the LCDIF. > > Signed-off-by: Marek Vasut <marex@denx.de> With the other rc358767 patches in place, this does the trick. Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> > --- > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: David Airlie <airlied@gmail.com> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Lukas F. Hartmann <lukas@mntmn.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Maxime Ripard <mripard@kernel.org> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Stefan Agner <stefan@agner.ch> > Cc: Thomas Zimmermann <tzimmermann@suse.de> > Cc: dri-devel@lists.freedesktop.org > Cc: imx@lists.linux.dev > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > --- > drivers/gpu/drm/mxsfb/lcdif_kms.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mxsfb/lcdif_kms.c b/drivers/gpu/drm/mxsfb/lcdif_kms.c > index 2541d2de4e45f..dbd42cc1da87f 100644 > --- a/drivers/gpu/drm/mxsfb/lcdif_kms.c > +++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c > @@ -407,8 +407,7 @@ static void lcdif_crtc_mode_set_nofb(struct drm_crtc_state *crtc_state, > struct drm_display_mode *m = &crtc_state->adjusted_mode; > > DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n", > - m->crtc_clock, > - (int)(clk_get_rate(lcdif->clk) / 1000)); > + m->clock, (int)(clk_get_rate(lcdif->clk) / 1000)); > DRM_DEV_DEBUG_DRIVER(drm->dev, "Bridge bus_flags: 0x%08X\n", > lcdif_crtc_state->bus_flags); > DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); > @@ -538,7 +537,7 @@ static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc, > struct drm_device *drm = lcdif->drm; > dma_addr_t paddr; > > - clk_set_rate(lcdif->clk, m->crtc_clock * 1000); > + clk_set_rate(lcdif->clk, m->clock * 1000); > > pm_runtime_get_sync(drm->dev); > >
On 6/24/24 11:19 AM, Alexander Stein wrote: > Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek Vasut: >> In case an upstream bridge modified the required clock frequency >> in its .atomic_check callback by setting adjusted_mode.clock , >> make sure that clock frequency is generated by the LCDIFv3 block. >> >> This is useful e.g. when LCDIFv3 feeds DSIM which feeds TC358767 >> with (e)DP output, where the TC358767 expects precise timing on >> its input side, the precise timing must be generated by the LCDIF. >> >> Signed-off-by: Marek Vasut <marex@denx.de> > > With the other rc358767 patches in place, this does the trick. > Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> I'll pick this up next week if there is no objection.
Hi Marek, On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: > On 6/24/24 11:19 AM, Alexander Stein wrote: > > Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek Vasut: > > > In case an upstream bridge modified the required clock frequency > > > in its .atomic_check callback by setting adjusted_mode.clock , > > > make sure that clock frequency is generated by the LCDIFv3 block. > > > > > > This is useful e.g. when LCDIFv3 feeds DSIM which feeds TC358767 > > > with (e)DP output, where the TC358767 expects precise timing on > > > its input side, the precise timing must be generated by the > > > LCDIF. > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > > With the other rc358767 patches in place, this does the trick. > > Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> > > I'll pick this up next week if there is no objection. Unfortunately, this has caused a regression that is present in v6.12- rc1 on the i.MX8MP PHYTEC Pollux using the arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. The display is the edt,etml1010g3dra panel, as per the upstream dts. We bisected to this commit, and reverting this change fixed the screen. We then tried to retest this on top of v6.12-rc2, and found we also had to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 ("clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate") alongside this. Reverting these two commits makes the display work again at -rc2. Do you have any suggestions on anything we might be missing on our end? Please let me know if there's anything you'd like me to test as I'm not sure what the underlying fault was here. Best wishes, Isaac
On 10/7/24 7:01 PM, Isaac Scott wrote: > Hi Marek, Hi, > On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: >> On 6/24/24 11:19 AM, Alexander Stein wrote: >>> Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek Vasut: >>>> In case an upstream bridge modified the required clock frequency >>>> in its .atomic_check callback by setting adjusted_mode.clock , >>>> make sure that clock frequency is generated by the LCDIFv3 block. >>>> >>>> This is useful e.g. when LCDIFv3 feeds DSIM which feeds TC358767 >>>> with (e)DP output, where the TC358767 expects precise timing on >>>> its input side, the precise timing must be generated by the >>>> LCDIF. >>>> >>>> Signed-off-by: Marek Vasut <marex@denx.de> >>> >>> With the other rc358767 patches in place, this does the trick. >>> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> >> >> I'll pick this up next week if there is no objection. > > Unfortunately, this has caused a regression that is present in v6.12- > rc1 on the i.MX8MP PHYTEC Pollux using the > arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. The > display is the edt,etml1010g3dra panel, as per the upstream dts. We > bisected to this commit, and reverting this change fixed the screen. > > We then tried to retest this on top of v6.12-rc2, and found we also had > to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 ("clk: imx: > clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate") > alongside this. Reverting these two commits makes the display work > again at -rc2. > > Do you have any suggestions on anything we might be missing on our end? > Please let me know if there's anything you'd like me to test as I'm not > sure what the underlying fault was here. I believe what is going on is that the LCDIF cannot configure its upstream clock because something else is already using those clock and it set those clock to a specific frequency. LCDIF is now trying to configure those clock to match the LVDS panel, and it fails, so it tries to set some approximate clock and that is not good enough for the LVDS panel. Can you share dump of /sys/kernel/debug/clk/clk_summary on failing and working system ? You might see the difference around the "video" clock. (I have seen this behavior before, the fix was usually a matter of moving one of the LCDIFs to another upstream clock like PLL3, so it can pick well matching output clock instead of some horrid approximation which then drives the panel likely out of specification)
On 10/8/24 12:07 PM, Isaac Scott wrote: > On Mon, 2024-10-07 at 20:06 +0200, Marek Vasut wrote: >> On 10/7/24 7:01 PM, Isaac Scott wrote: >>> Hi Marek, >> >> Hi, >> >>> On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: >>>> On 6/24/24 11:19 AM, Alexander Stein wrote: >>>>> Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek Vasut: >>>>>> In case an upstream bridge modified the required clock >>>>>> frequency >>>>>> in its .atomic_check callback by setting adjusted_mode.clock >>>>>> , >>>>>> make sure that clock frequency is generated by the LCDIFv3 >>>>>> block. >>>>>> >>>>>> This is useful e.g. when LCDIFv3 feeds DSIM which feeds >>>>>> TC358767 >>>>>> with (e)DP output, where the TC358767 expects precise timing >>>>>> on >>>>>> its input side, the precise timing must be generated by the >>>>>> LCDIF. >>>>>> >>>>>> Signed-off-by: Marek Vasut <marex@denx.de> >>>>> >>>>> With the other rc358767 patches in place, this does the trick. >>>>> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> >>>> >>>> I'll pick this up next week if there is no objection. >>> >>> Unfortunately, this has caused a regression that is present in >>> v6.12- >>> rc1 on the i.MX8MP PHYTEC Pollux using the >>> arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. The >>> display is the edt,etml1010g3dra panel, as per the upstream dts. We >>> bisected to this commit, and reverting this change fixed the >>> screen. >>> >>> We then tried to retest this on top of v6.12-rc2, and found we also >>> had >>> to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 ("clk: >>> imx: >>> clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate") >>> alongside this. Reverting these two commits makes the display work >>> again at -rc2. >>> >>> Do you have any suggestions on anything we might be missing on our >>> end? >>> Please let me know if there's anything you'd like me to test as I'm >>> not >>> sure what the underlying fault was here. >> I believe what is going on is that the LCDIF cannot configure its >> upstream clock because something else is already using those clock >> and >> it set those clock to a specific frequency. LCDIF is now trying to >> configure those clock to match the LVDS panel, and it fails, so it >> tries >> to set some approximate clock and that is not good enough for the >> LVDS >> panel. >> >> Can you share dump of /sys/kernel/debug/clk/clk_summary on failing >> and >> working system ? You might see the difference around the "video" >> clock. >> >> (I have seen this behavior before, the fix was usually a matter of >> moving one of the LCDIFs to another upstream clock like PLL3, so it >> can >> pick well matching output clock instead of some horrid approximation >> which then drives the panel likely out of specification) > > Hi Marek, > > Please find attached the clk_summary for v6.12-rc2 before and after the > reversion (the one after the reversion is 6.12-rc2_summary_postfix). How come "media_mipi_phy1_ref" is on Video PLL1 before the revert ? Does it start working if you move "media_mipi_phy1_ref" to osc_24m ? (probably not) Also, why is the LDB configured to 74 MHz instead of 519 MHz now ? That is really odd. I'll see if I can reproduce this later today.
On 10/8/24 12:07 PM, Isaac Scott wrote: > On Mon, 2024-10-07 at 20:06 +0200, Marek Vasut wrote: >> On 10/7/24 7:01 PM, Isaac Scott wrote: >>> Hi Marek, >> >> Hi, >> >>> On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: >>>> On 6/24/24 11:19 AM, Alexander Stein wrote: >>>>> Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek Vasut: >>>>>> In case an upstream bridge modified the required clock >>>>>> frequency >>>>>> in its .atomic_check callback by setting adjusted_mode.clock >>>>>> , >>>>>> make sure that clock frequency is generated by the LCDIFv3 >>>>>> block. >>>>>> >>>>>> This is useful e.g. when LCDIFv3 feeds DSIM which feeds >>>>>> TC358767 >>>>>> with (e)DP output, where the TC358767 expects precise timing >>>>>> on >>>>>> its input side, the precise timing must be generated by the >>>>>> LCDIF. >>>>>> >>>>>> Signed-off-by: Marek Vasut <marex@denx.de> >>>>> >>>>> With the other rc358767 patches in place, this does the trick. >>>>> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> >>>> >>>> I'll pick this up next week if there is no objection. >>> >>> Unfortunately, this has caused a regression that is present in >>> v6.12- >>> rc1 on the i.MX8MP PHYTEC Pollux using the >>> arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. The >>> display is the edt,etml1010g3dra panel, as per the upstream dts. We >>> bisected to this commit, and reverting this change fixed the >>> screen. >>> >>> We then tried to retest this on top of v6.12-rc2, and found we also >>> had >>> to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 ("clk: >>> imx: >>> clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate") >>> alongside this. Reverting these two commits makes the display work >>> again at -rc2. >>> >>> Do you have any suggestions on anything we might be missing on our >>> end? >>> Please let me know if there's anything you'd like me to test as I'm >>> not >>> sure what the underlying fault was here. >> I believe what is going on is that the LCDIF cannot configure its >> upstream clock because something else is already using those clock >> and >> it set those clock to a specific frequency. LCDIF is now trying to >> configure those clock to match the LVDS panel, and it fails, so it >> tries >> to set some approximate clock and that is not good enough for the >> LVDS >> panel. >> >> Can you share dump of /sys/kernel/debug/clk/clk_summary on failing >> and >> working system ? You might see the difference around the "video" >> clock. >> >> (I have seen this behavior before, the fix was usually a matter of >> moving one of the LCDIFs to another upstream clock like PLL3, so it >> can >> pick well matching output clock instead of some horrid approximation >> which then drives the panel likely out of specification) > > Hi Marek, > > Please find attached the clk_summary for v6.12-rc2 before and after the > reversion (the one after the reversion is 6.12-rc2_summary_postfix). Thank you, this helped greatly. I believe I know why it used to kind-of work for you, but I'm afraid this used to work by sheer chance and it does not really work correctly for the panel you use, even if the panel likely does show the correct content. But, there is a way to make it work properly for the panel you use. First of all, the pixel clock never really matched the panel-simple.c pixel clock for the edt_etml1010g3dra_timing: $ grep '\<media_disp2_pix\>' 6.12-rc2_summary_postfix media_disp2_pix 1 1 0 74250000 ... ^^^^^^^^ $ grep -A 1 edt_etml1010g3dra_timing drivers/gpu/drm/panel/panel-simple.c static const struct display_timing edt_etml1010g3dra_timing = { .pixelclock = { 66300000, 72400000, 78900000 }, ^^^^^^^^ The pixel clock are within tolerance, but there is a discrepancy 74250000 != 72400000 . Since commit 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB nodes") the IMX8MP_VIDEO_PLL1_OUT is set to a very specific frequency of 1039500000 Hz, which tidily divides by 2 to 519750000 Hz (which is your LVDS serializer frequency) and divides by 7 to 74250000 Hz which is your LCDIF pixel clock. This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: &media_blk_ctrl { // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) // there is no need to multiply the clock by * 2 assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; }; Can you please test whether this works and the pixel clock are accurate in /sys/kernel/debug/clk/clk_summary ? Now ... as for the LVDS serializer clock ... that is more complicated. The LCDIF driver does its .atomic_enable first , configures the pixel clock (and the Video PLL now) and enables the clock. The LVDS LDB serializer driver does its .atomic_enable second and cannot reconfigure the clock anymore, the Video PLL is stuck at /7 rate set by LCDIF driver and won't budge because the clock are already enabled. I'm currently trying to figure out if this can be improved somehow, but I believe that would be material for next release.
On Tue, 2024-10-08 at 23:48 +0200, Marek Vasut wrote: > On 10/8/24 12:07 PM, Isaac Scott wrote: > > On Mon, 2024-10-07 at 20:06 +0200, Marek Vasut wrote: > > > On 10/7/24 7:01 PM, Isaac Scott wrote: > > > > Hi Marek, > > > > > > Hi, > > > > > > > On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: > > > > > On 6/24/24 11:19 AM, Alexander Stein wrote: > > > > > > Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek > > > > > > Vasut: > > > > > > > In case an upstream bridge modified the required clock > > > > > > > frequency > > > > > > > in its .atomic_check callback by setting > > > > > > > adjusted_mode.clock > > > > > > > , > > > > > > > make sure that clock frequency is generated by the > > > > > > > LCDIFv3 > > > > > > > block. > > > > > > > > > > > > > > This is useful e.g. when LCDIFv3 feeds DSIM which feeds > > > > > > > TC358767 > > > > > > > with (e)DP output, where the TC358767 expects precise > > > > > > > timing > > > > > > > on > > > > > > > its input side, the precise timing must be generated by > > > > > > > the > > > > > > > LCDIF. > > > > > > > > > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > > > > > > > > > > With the other rc358767 patches in place, this does the > > > > > > trick. > > > > > > Reviewed-by: Alexander Stein > > > > > > <alexander.stein@ew.tq-group.com> > > > > > > > > > > I'll pick this up next week if there is no objection. > > > > > > > > Unfortunately, this has caused a regression that is present in > > > > v6.12- > > > > rc1 on the i.MX8MP PHYTEC Pollux using the > > > > arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. > > > > The > > > > display is the edt,etml1010g3dra panel, as per the upstream > > > > dts. We > > > > bisected to this commit, and reverting this change fixed the > > > > screen. > > > > > > > > We then tried to retest this on top of v6.12-rc2, and found we > > > > also > > > > had > > > > to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 > > > > ("clk: > > > > imx: > > > > clk-imx8mp: Allow media_disp pixel clock reconfigure parent > > > > rate") > > > > alongside this. Reverting these two commits makes the display > > > > work > > > > again at -rc2. > > > > > > > > Do you have any suggestions on anything we might be missing on > > > > our > > > > end? > > > > Please let me know if there's anything you'd like me to test as > > > > I'm > > > > not > > > > sure what the underlying fault was here. > > > I believe what is going on is that the LCDIF cannot configure its > > > upstream clock because something else is already using those > > > clock > > > and > > > it set those clock to a specific frequency. LCDIF is now trying > > > to > > > configure those clock to match the LVDS panel, and it fails, so > > > it > > > tries > > > to set some approximate clock and that is not good enough for the > > > LVDS > > > panel. > > > > > > Can you share dump of /sys/kernel/debug/clk/clk_summary on > > > failing > > > and > > > working system ? You might see the difference around the "video" > > > clock. > > > > > > (I have seen this behavior before, the fix was usually a matter > > > of > > > moving one of the LCDIFs to another upstream clock like PLL3, so > > > it > > > can > > > pick well matching output clock instead of some horrid > > > approximation > > > which then drives the panel likely out of specification) > > > > Hi Marek, > > > > Please find attached the clk_summary for v6.12-rc2 before and after > > the > > reversion (the one after the reversion is 6.12- > > rc2_summary_postfix). > Thank you, this helped greatly. > > I believe I know why it used to kind-of work for you, but I'm afraid > this used to work by sheer chance and it does not really work > correctly > for the panel you use, even if the panel likely does show the correct > content. But, there is a way to make it work properly for the panel > you use. > > First of all, the pixel clock never really matched the panel-simple.c > pixel clock for the edt_etml1010g3dra_timing: > > $ grep '\<media_disp2_pix\>' 6.12-rc2_summary_postfix > media_disp2_pix 1 1 0 74250000 ... > ^^^^^^^^ > > $ grep -A 1 edt_etml1010g3dra_timing drivers/gpu/drm/panel/panel- > simple.c > static const struct display_timing edt_etml1010g3dra_timing = { > .pixelclock = { 66300000, 72400000, 78900000 }, > ^^^^^^^^ > > The pixel clock are within tolerance, but there is a discrepancy > 74250000 != 72400000 . > > Since commit 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB > nodes") > the IMX8MP_VIDEO_PLL1_OUT is set to a very specific frequency of > 1039500000 Hz, which tidily divides by 2 to 519750000 Hz (which is > your > LVDS serializer frequency) and divides by 7 to 74250000 Hz which is > your > LCDIF pixel clock. > > This Video PLL1 configuration since moved to &media_blk_ctrl {} , but > it > is still in the imx8mp.dtsi . Therefore, to make your panel work at > the > correct desired pixel clock frequency instead of some random one > inherited from imx8mp.dtsi, add the following to the pollux DT, I > believe that will fix the problem and is the correct fix: > > &media_blk_ctrl { > // 506800000 = 72400000 * 7 (for single-link LVDS, this is > enough) > // there is no need to multiply the clock by * 2 > assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, > <500000000>, <506800000>; > }; > > Can you please test whether this works and the pixel clock are > accurate > in /sys/kernel/debug/clk/clk_summary ? Interestingly, after making the change you suggested to imx8mp- phyboard-pollux-rdk.dts before the two reversions, the display now seems to work. Please see below for the relevant section of the new clk_summary referring to media_disp2_pix: video_pll1_ref_sel 1 1 0 24000000 0 0 50000 Y deviceless no_connection_id video_pll1 1 1 0 506800000 0 0 50000 Y deviceless no_connection_ video_pll1_bypass 1 1 0 506800000 0 0 50000 Y deviceless no_connecti video_pll1_out 2 2 0 506800000 0 0 50000 Y deviceless no_conne media_ldb 1 1 0 506800000 0 0 50000 Y deviceless no_co media_ldb_root_clk 1 1 0 506800000 0 0 50000 Y 32ec0000.blk-ctrl:bridge@5c l deviceless no media_disp2_pix 1 1 0 72400000 0 0 50000 Y deviceless no_co media_disp2_pix_root_clk 1 1 0 72400000 0 0 50000 Y 32e90000.display-controller 32ec0000.blk-ctrl di deviceless no media_disp1_pix 0 0 0 506800000 0 0 50000 N deviceless no_co media_disp1_pix_root_clk 0 0 0 506800000 0 0 50000 N 32ec0000.blk-ctrl deviceless no media_mipi_phy1_ref 0 0 0 23036364 0 0 50000 N deviceless no_co media_mipi_phy1_ref_root 0 0 0 23036364 0 0 50000 N 32ec0000.blk-ctrl The media_disp2_pix clock now seems to be correct at 724000000 after your changes.
On 10/9/24 11:55 AM, Isaac Scott wrote: > On Tue, 2024-10-08 at 23:48 +0200, Marek Vasut wrote: >> On 10/8/24 12:07 PM, Isaac Scott wrote: >>> On Mon, 2024-10-07 at 20:06 +0200, Marek Vasut wrote: >>>> On 10/7/24 7:01 PM, Isaac Scott wrote: >>>>> Hi Marek, >>>> >>>> Hi, >>>> >>>>> On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: >>>>>> On 6/24/24 11:19 AM, Alexander Stein wrote: >>>>>>> Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek >>>>>>> Vasut: >>>>>>>> In case an upstream bridge modified the required clock >>>>>>>> frequency >>>>>>>> in its .atomic_check callback by setting >>>>>>>> adjusted_mode.clock >>>>>>>> , >>>>>>>> make sure that clock frequency is generated by the >>>>>>>> LCDIFv3 >>>>>>>> block. >>>>>>>> >>>>>>>> This is useful e.g. when LCDIFv3 feeds DSIM which feeds >>>>>>>> TC358767 >>>>>>>> with (e)DP output, where the TC358767 expects precise >>>>>>>> timing >>>>>>>> on >>>>>>>> its input side, the precise timing must be generated by >>>>>>>> the >>>>>>>> LCDIF. >>>>>>>> >>>>>>>> Signed-off-by: Marek Vasut <marex@denx.de> >>>>>>> >>>>>>> With the other rc358767 patches in place, this does the >>>>>>> trick. >>>>>>> Reviewed-by: Alexander Stein >>>>>>> <alexander.stein@ew.tq-group.com> >>>>>> >>>>>> I'll pick this up next week if there is no objection. >>>>> >>>>> Unfortunately, this has caused a regression that is present in >>>>> v6.12- >>>>> rc1 on the i.MX8MP PHYTEC Pollux using the >>>>> arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. >>>>> The >>>>> display is the edt,etml1010g3dra panel, as per the upstream >>>>> dts. We >>>>> bisected to this commit, and reverting this change fixed the >>>>> screen. >>>>> >>>>> We then tried to retest this on top of v6.12-rc2, and found we >>>>> also >>>>> had >>>>> to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 >>>>> ("clk: >>>>> imx: >>>>> clk-imx8mp: Allow media_disp pixel clock reconfigure parent >>>>> rate") >>>>> alongside this. Reverting these two commits makes the display >>>>> work >>>>> again at -rc2. >>>>> >>>>> Do you have any suggestions on anything we might be missing on >>>>> our >>>>> end? >>>>> Please let me know if there's anything you'd like me to test as >>>>> I'm >>>>> not >>>>> sure what the underlying fault was here. >>>> I believe what is going on is that the LCDIF cannot configure its >>>> upstream clock because something else is already using those >>>> clock >>>> and >>>> it set those clock to a specific frequency. LCDIF is now trying >>>> to >>>> configure those clock to match the LVDS panel, and it fails, so >>>> it >>>> tries >>>> to set some approximate clock and that is not good enough for the >>>> LVDS >>>> panel. >>>> >>>> Can you share dump of /sys/kernel/debug/clk/clk_summary on >>>> failing >>>> and >>>> working system ? You might see the difference around the "video" >>>> clock. >>>> >>>> (I have seen this behavior before, the fix was usually a matter >>>> of >>>> moving one of the LCDIFs to another upstream clock like PLL3, so >>>> it >>>> can >>>> pick well matching output clock instead of some horrid >>>> approximation >>>> which then drives the panel likely out of specification) >>> >>> Hi Marek, >>> >>> Please find attached the clk_summary for v6.12-rc2 before and after >>> the >>> reversion (the one after the reversion is 6.12- >>> rc2_summary_postfix). >> Thank you, this helped greatly. >> >> I believe I know why it used to kind-of work for you, but I'm afraid >> this used to work by sheer chance and it does not really work >> correctly >> for the panel you use, even if the panel likely does show the correct >> content. But, there is a way to make it work properly for the panel >> you use. >> >> First of all, the pixel clock never really matched the panel-simple.c >> pixel clock for the edt_etml1010g3dra_timing: >> >> $ grep '\<media_disp2_pix\>' 6.12-rc2_summary_postfix >> media_disp2_pix 1 1 0 74250000 ... >> ^^^^^^^^ >> >> $ grep -A 1 edt_etml1010g3dra_timing drivers/gpu/drm/panel/panel- >> simple.c >> static const struct display_timing edt_etml1010g3dra_timing = { >> .pixelclock = { 66300000, 72400000, 78900000 }, >> ^^^^^^^^ >> >> The pixel clock are within tolerance, but there is a discrepancy >> 74250000 != 72400000 . >> >> Since commit 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB >> nodes") >> the IMX8MP_VIDEO_PLL1_OUT is set to a very specific frequency of >> 1039500000 Hz, which tidily divides by 2 to 519750000 Hz (which is >> your >> LVDS serializer frequency) and divides by 7 to 74250000 Hz which is >> your >> LCDIF pixel clock. >> >> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but >> it >> is still in the imx8mp.dtsi . Therefore, to make your panel work at >> the >> correct desired pixel clock frequency instead of some random one >> inherited from imx8mp.dtsi, add the following to the pollux DT, I >> believe that will fix the problem and is the correct fix: >> >> &media_blk_ctrl { >> // 506800000 = 72400000 * 7 (for single-link LVDS, this is >> enough) >> // there is no need to multiply the clock by * 2 >> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, >> <500000000>, <506800000>; >> }; >> >> Can you please test whether this works and the pixel clock are >> accurate >> in /sys/kernel/debug/clk/clk_summary ? > > Interestingly, after making the change you suggested to imx8mp- > phyboard-pollux-rdk.dts before the two reversions, the display now > seems to work. Please see below for the relevant section of the new > clk_summary referring to media_disp2_pix: > > video_pll1_ref_sel 1 1 0 24000000 > 0 0 50000 Y deviceless > no_connection_id > video_pll1 1 1 0 > 506800000 0 0 50000 Y deviceless > no_connection_ > video_pll1_bypass 1 1 0 > 506800000 0 0 50000 Y deviceless > no_connecti > video_pll1_out 2 2 0 > 506800000 0 0 50000 Y deviceless > no_conne > media_ldb 1 1 0 > 506800000 0 0 50000 Y deviceless > no_co > media_ldb_root_clk 1 1 0 > 506800000 0 0 50000 Y > 32ec0000.blk-ctrl:bridge@5c l > > deviceless no > media_disp2_pix 1 1 0 72400000 > 0 0 50000 Y deviceless > no_co > media_disp2_pix_root_clk 1 1 0 > 72400000 0 0 50000 Y > 32e90000.display-controller > > 32ec0000.blk-ctrl di > > deviceless no > media_disp1_pix 0 0 0 > 506800000 0 0 50000 N deviceless > no_co > media_disp1_pix_root_clk 0 0 0 > 506800000 0 0 50000 N > 32ec0000.blk-ctrl > > deviceless no > media_mipi_phy1_ref 0 0 0 23036364 > 0 0 50000 N deviceless > no_co > media_mipi_phy1_ref_root 0 0 0 > 23036364 0 0 50000 N > 32ec0000.blk-ctrl > > The media_disp2_pix clock now seems to be correct at 724000000 after > your changes. Do you want to submit the DT patch with correct Fixes: tag ? :)
On Wed, 2024-10-09 at 17:47 +0200, Marek Vasut wrote: > On 10/9/24 11:55 AM, Isaac Scott wrote: > > On Tue, 2024-10-08 at 23:48 +0200, Marek Vasut wrote: > > > On 10/8/24 12:07 PM, Isaac Scott wrote: > > > > On Mon, 2024-10-07 at 20:06 +0200, Marek Vasut wrote: > > > > > On 10/7/24 7:01 PM, Isaac Scott wrote: > > > > > > Hi Marek, > > > > > > > > > > Hi, > > > > > > > > > > > On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: > > > > > > > On 6/24/24 11:19 AM, Alexander Stein wrote: > > > > > > > > Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek > > > > > > > > Vasut: > > > > > > > > > In case an upstream bridge modified the required > > > > > > > > > clock > > > > > > > > > frequency > > > > > > > > > in its .atomic_check callback by setting > > > > > > > > > adjusted_mode.clock > > > > > > > > > , > > > > > > > > > make sure that clock frequency is generated by the > > > > > > > > > LCDIFv3 > > > > > > > > > block. > > > > > > > > > > > > > > > > > > This is useful e.g. when LCDIFv3 feeds DSIM which > > > > > > > > > feeds > > > > > > > > > TC358767 > > > > > > > > > with (e)DP output, where the TC358767 expects precise > > > > > > > > > timing > > > > > > > > > on > > > > > > > > > its input side, the precise timing must be generated > > > > > > > > > by > > > > > > > > > the > > > > > > > > > LCDIF. > > > > > > > > > > > > > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > > > > > > > > > > > > > > With the other rc358767 patches in place, this does the > > > > > > > > trick. > > > > > > > > Reviewed-by: Alexander Stein > > > > > > > > <alexander.stein@ew.tq-group.com> > > > > > > > > > > > > > > I'll pick this up next week if there is no objection. > > > > > > > > > > > > Unfortunately, this has caused a regression that is present > > > > > > in > > > > > > v6.12- > > > > > > rc1 on the i.MX8MP PHYTEC Pollux using the > > > > > > arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux- > > > > > > rdk.dts. > > > > > > The > > > > > > display is the edt,etml1010g3dra panel, as per the upstream > > > > > > dts. We > > > > > > bisected to this commit, and reverting this change fixed > > > > > > the > > > > > > screen. > > > > > > > > > > > > We then tried to retest this on top of v6.12-rc2, and found > > > > > > we > > > > > > also > > > > > > had > > > > > > to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 > > > > > > ("clk: > > > > > > imx: > > > > > > clk-imx8mp: Allow media_disp pixel clock reconfigure parent > > > > > > rate") > > > > > > alongside this. Reverting these two commits makes the > > > > > > display > > > > > > work > > > > > > again at -rc2. > > > > > > > > > > > > Do you have any suggestions on anything we might be missing > > > > > > on > > > > > > our > > > > > > end? > > > > > > Please let me know if there's anything you'd like me to > > > > > > test as > > > > > > I'm > > > > > > not > > > > > > sure what the underlying fault was here. > > > > > I believe what is going on is that the LCDIF cannot configure > > > > > its > > > > > upstream clock because something else is already using those > > > > > clock > > > > > and > > > > > it set those clock to a specific frequency. LCDIF is now > > > > > trying > > > > > to > > > > > configure those clock to match the LVDS panel, and it fails, > > > > > so > > > > > it > > > > > tries > > > > > to set some approximate clock and that is not good enough for > > > > > the > > > > > LVDS > > > > > panel. > > > > > > > > > > Can you share dump of /sys/kernel/debug/clk/clk_summary on > > > > > failing > > > > > and > > > > > working system ? You might see the difference around the > > > > > "video" > > > > > clock. > > > > > > > > > > (I have seen this behavior before, the fix was usually a > > > > > matter > > > > > of > > > > > moving one of the LCDIFs to another upstream clock like PLL3, > > > > > so > > > > > it > > > > > can > > > > > pick well matching output clock instead of some horrid > > > > > approximation > > > > > which then drives the panel likely out of specification) > > > > > > > > Hi Marek, > > > > > > > > Please find attached the clk_summary for v6.12-rc2 before and > > > > after > > > > the > > > > reversion (the one after the reversion is 6.12- > > > > rc2_summary_postfix). > > > Thank you, this helped greatly. > > > > > > I believe I know why it used to kind-of work for you, but I'm > > > afraid > > > this used to work by sheer chance and it does not really work > > > correctly > > > for the panel you use, even if the panel likely does show the > > > correct > > > content. But, there is a way to make it work properly for the > > > panel > > > you use. > > > > > > First of all, the pixel clock never really matched the panel- > > > simple.c > > > pixel clock for the edt_etml1010g3dra_timing: > > > > > > $ grep '\<media_disp2_pix\>' 6.12-rc2_summary_postfix > > > media_disp2_pix 1 1 0 74250000 ... > > > ^^^^^^^^ > > > > > > $ grep -A 1 edt_etml1010g3dra_timing drivers/gpu/drm/panel/panel- > > > simple.c > > > static const struct display_timing edt_etml1010g3dra_timing = { > > > .pixelclock = { 66300000, 72400000, 78900000 }, > > > ^^^^^^^^ > > > > > > The pixel clock are within tolerance, but there is a discrepancy > > > 74250000 != 72400000 . > > > > > > Since commit 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB > > > nodes") > > > the IMX8MP_VIDEO_PLL1_OUT is set to a very specific frequency of > > > 1039500000 Hz, which tidily divides by 2 to 519750000 Hz (which > > > is > > > your > > > LVDS serializer frequency) and divides by 7 to 74250000 Hz which > > > is > > > your > > > LCDIF pixel clock. > > > > > > This Video PLL1 configuration since moved to &media_blk_ctrl {} , > > > but > > > it > > > is still in the imx8mp.dtsi . Therefore, to make your panel work > > > at > > > the > > > correct desired pixel clock frequency instead of some random one > > > inherited from imx8mp.dtsi, add the following to the pollux DT, I > > > believe that will fix the problem and is the correct fix: > > > > > > &media_blk_ctrl { > > > // 506800000 = 72400000 * 7 (for single-link LVDS, this is > > > enough) > > > // there is no need to multiply the clock by * 2 > > > assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, > > > <500000000>, <506800000>; > > > }; > > > > > > Can you please test whether this works and the pixel clock are > > > accurate > > > in /sys/kernel/debug/clk/clk_summary ? > > > > Interestingly, after making the change you suggested to imx8mp- > > phyboard-pollux-rdk.dts before the two reversions, the display now > > seems to work. Please see below for the relevant section of the new > > clk_summary referring to media_disp2_pix: > > > > video_pll1_ref_sel 1 1 0 24000000 > > 0 0 50000 Y deviceless > > no_connection_id > > video_pll1 1 1 0 > > 506800000 0 0 50000 Y deviceless > > no_connection_ > > video_pll1_bypass 1 1 0 > > 506800000 0 0 50000 Y deviceless > > no_connecti > > video_pll1_out 2 2 0 > > 506800000 0 0 50000 Y deviceless > > no_conne > > media_ldb 1 1 0 > > 506800000 0 0 50000 Y > > deviceless > > no_co > > media_ldb_root_clk 1 1 0 > > 506800000 0 0 50000 Y > > 32ec0000.blk-ctrl:bridge@5c l > > > > > > deviceless no > > media_disp2_pix 1 1 0 > > 72400000 > > 0 0 50000 Y deviceless > > no_co > > media_disp2_pix_root_clk 1 1 0 > > 72400000 0 0 50000 Y > > 32e90000.display-controller > > > > > > 32ec0000.blk-ctrl di > > > > > > deviceless no > > media_disp1_pix 0 0 0 > > 506800000 0 0 50000 N > > deviceless > > no_co > > media_disp1_pix_root_clk 0 0 0 > > 506800000 0 0 50000 N > > 32ec0000.blk-ctrl > > > > > > deviceless no > > media_mipi_phy1_ref 0 0 0 > > 23036364 > > 0 0 50000 N deviceless > > no_co > > media_mipi_phy1_ref_root 0 0 0 > > 23036364 0 0 50000 N > > 32ec0000.blk-ctrl > > > > The media_disp2_pix clock now seems to be correct at 724000000 > > after > > your changes. > > Do you want to submit the DT patch with correct Fixes: tag ? :) I thought this wasn't needed with the other two patches?
On 10/9/24 5:58 PM, Isaac Scott wrote: [...] >>> media_mipi_phy1_ref 0 0 0 >>> 23036364 >>> 0 0 50000 N deviceless >>> no_co >>> media_mipi_phy1_ref_root 0 0 0 >>> 23036364 0 0 50000 N >>> 32ec0000.blk-ctrl >>> >>> The media_disp2_pix clock now seems to be correct at 724000000 >>> after >>> your changes. >> >> Do you want to submit the DT patch with correct Fixes: tag ? :) > > I thought this wasn't needed with the other two patches? The DT change is not needed with the other patches, however, I believe the DT change is the correct fix for current Linux 6.12-rc and the two patches are feature development for the Linux 6.13.y cycle.
On 10/09/2024, Marek Vasut wrote: > On 10/8/24 12:07 PM, Isaac Scott wrote: >> On Mon, 2024-10-07 at 20:06 +0200, Marek Vasut wrote: >>> On 10/7/24 7:01 PM, Isaac Scott wrote: >>>> Hi Marek, >>> >>> Hi, >>> >>>> On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: >>>>> On 6/24/24 11:19 AM, Alexander Stein wrote: >>>>>> Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek Vasut: >>>>>>> In case an upstream bridge modified the required clock >>>>>>> frequency >>>>>>> in its .atomic_check callback by setting adjusted_mode.clock >>>>>>> , >>>>>>> make sure that clock frequency is generated by the LCDIFv3 >>>>>>> block. >>>>>>> >>>>>>> This is useful e.g. when LCDIFv3 feeds DSIM which feeds >>>>>>> TC358767 >>>>>>> with (e)DP output, where the TC358767 expects precise timing >>>>>>> on >>>>>>> its input side, the precise timing must be generated by the >>>>>>> LCDIF. >>>>>>> >>>>>>> Signed-off-by: Marek Vasut <marex@denx.de> >>>>>> >>>>>> With the other rc358767 patches in place, this does the trick. >>>>>> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> >>>>> >>>>> I'll pick this up next week if there is no objection. >>>> >>>> Unfortunately, this has caused a regression that is present in >>>> v6.12- >>>> rc1 on the i.MX8MP PHYTEC Pollux using the >>>> arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. The >>>> display is the edt,etml1010g3dra panel, as per the upstream dts. We >>>> bisected to this commit, and reverting this change fixed the >>>> screen. >>>> >>>> We then tried to retest this on top of v6.12-rc2, and found we also >>>> had >>>> to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 ("clk: >>>> imx: >>>> clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate") >>>> alongside this. Reverting these two commits makes the display work >>>> again at -rc2. >>>> >>>> Do you have any suggestions on anything we might be missing on our >>>> end? >>>> Please let me know if there's anything you'd like me to test as I'm >>>> not >>>> sure what the underlying fault was here. >>> I believe what is going on is that the LCDIF cannot configure its >>> upstream clock because something else is already using those clock >>> and >>> it set those clock to a specific frequency. LCDIF is now trying to >>> configure those clock to match the LVDS panel, and it fails, so it >>> tries >>> to set some approximate clock and that is not good enough for the >>> LVDS >>> panel. >>> >>> Can you share dump of /sys/kernel/debug/clk/clk_summary on failing >>> and >>> working system ? You might see the difference around the "video" >>> clock. >>> >>> (I have seen this behavior before, the fix was usually a matter of >>> moving one of the LCDIFs to another upstream clock like PLL3, so it >>> can >>> pick well matching output clock instead of some horrid approximation >>> which then drives the panel likely out of specification) >> >> Hi Marek, >> >> Please find attached the clk_summary for v6.12-rc2 before and after the >> reversion (the one after the reversion is 6.12-rc2_summary_postfix). > Thank you, this helped greatly. > > I believe I know why it used to kind-of work for you, but I'm afraid this used to work by sheer chance and it does not really work correctly for the panel you use, even if the panel likely does show the correct content. But, there is a way to make it work properly for the panel you use. > > First of all, the pixel clock never really matched the panel-simple.c pixel clock for the edt_etml1010g3dra_timing: > > $ grep '\<media_disp2_pix\>' 6.12-rc2_summary_postfix > media_disp2_pix 1 1 0 74250000 ... > ^^^^^^^^ > > $ grep -A 1 edt_etml1010g3dra_timing drivers/gpu/drm/panel/panel-simple.c > static const struct display_timing edt_etml1010g3dra_timing = { > .pixelclock = { 66300000, 72400000, 78900000 }, > ^^^^^^^^ > > The pixel clock are within tolerance, but there is a discrepancy 74250000 != 72400000 . > > Since commit 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB nodes") the IMX8MP_VIDEO_PLL1_OUT is set to a very specific frequency of 1039500000 Hz, which tidily divides by 2 to 519750000 Hz (which is your LVDS serializer frequency) and divides by 7 to 74250000 Hz which is your LCDIF pixel clock. > > This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: > > &media_blk_ctrl { > // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) > // there is no need to multiply the clock by * 2 > assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; This assigns "video_pll1" clock rate to 506.8MHz which is currently not listed in imx_pll1443x_tbl[]. Does the below patch[1] fix the regression issue? It explicitly sets the clock frequency of the panel timing to 74.25MHz. [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 > }; > > Can you please test whether this works and the pixel clock are accurate in /sys/kernel/debug/clk/clk_summary ? > > Now ... as for the LVDS serializer clock ... that is more complicated. > > The LCDIF driver does its .atomic_enable first , configures the pixel clock (and the Video PLL now) and enables the clock. The LVDS LDB serializer driver does its .atomic_enable second and cannot reconfigure the clock anymore, the Video PLL is stuck at /7 rate set by LCDIF driver and won't budge because the clock are already enabled. I'm currently trying to figure out if this can be improved somehow, but I believe that would be material for next release. >
On Thu, 2024-10-10 at 13:31 +0800, Liu Ying wrote: > On 10/09/2024, Marek Vasut wrote: > > On 10/8/24 12:07 PM, Isaac Scott wrote: > > > On Mon, 2024-10-07 at 20:06 +0200, Marek Vasut wrote: > > > > On 10/7/24 7:01 PM, Isaac Scott wrote: > > > > > Hi Marek, > > > > > > > > Hi, > > > > > > > > > On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: > > > > > > On 6/24/24 11:19 AM, Alexander Stein wrote: > > > > > > > Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek > > > > > > > Vasut: > > > > > > > > In case an upstream bridge modified the required clock > > > > > > > > frequency > > > > > > > > in its .atomic_check callback by setting > > > > > > > > adjusted_mode.clock > > > > > > > > , > > > > > > > > make sure that clock frequency is generated by the > > > > > > > > LCDIFv3 > > > > > > > > block. > > > > > > > > > > > > > > > > This is useful e.g. when LCDIFv3 feeds DSIM which feeds > > > > > > > > TC358767 > > > > > > > > with (e)DP output, where the TC358767 expects precise > > > > > > > > timing > > > > > > > > on > > > > > > > > its input side, the precise timing must be generated by > > > > > > > > the > > > > > > > > LCDIF. > > > > > > > > > > > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > > > > > > > > > > > > With the other rc358767 patches in place, this does the > > > > > > > trick. > > > > > > > Reviewed-by: Alexander Stein > > > > > > > <alexander.stein@ew.tq-group.com> > > > > > > > > > > > > I'll pick this up next week if there is no objection. > > > > > > > > > > Unfortunately, this has caused a regression that is present > > > > > in > > > > > v6.12- > > > > > rc1 on the i.MX8MP PHYTEC Pollux using the > > > > > arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. > > > > > The > > > > > display is the edt,etml1010g3dra panel, as per the upstream > > > > > dts. We > > > > > bisected to this commit, and reverting this change fixed the > > > > > screen. > > > > > > > > > > We then tried to retest this on top of v6.12-rc2, and found > > > > > we also > > > > > had > > > > > to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 > > > > > ("clk: > > > > > imx: > > > > > clk-imx8mp: Allow media_disp pixel clock reconfigure parent > > > > > rate") > > > > > alongside this. Reverting these two commits makes the display > > > > > work > > > > > again at -rc2. > > > > > > > > > > Do you have any suggestions on anything we might be missing > > > > > on our > > > > > end? > > > > > Please let me know if there's anything you'd like me to test > > > > > as I'm > > > > > not > > > > > sure what the underlying fault was here. > > > > I believe what is going on is that the LCDIF cannot configure > > > > its > > > > upstream clock because something else is already using those > > > > clock > > > > and > > > > it set those clock to a specific frequency. LCDIF is now trying > > > > to > > > > configure those clock to match the LVDS panel, and it fails, so > > > > it > > > > tries > > > > to set some approximate clock and that is not good enough for > > > > the > > > > LVDS > > > > panel. > > > > > > > > Can you share dump of /sys/kernel/debug/clk/clk_summary on > > > > failing > > > > and > > > > working system ? You might see the difference around the > > > > "video" > > > > clock. > > > > > > > > (I have seen this behavior before, the fix was usually a matter > > > > of > > > > moving one of the LCDIFs to another upstream clock like PLL3, > > > > so it > > > > can > > > > pick well matching output clock instead of some horrid > > > > approximation > > > > which then drives the panel likely out of specification) > > > > > > Hi Marek, > > > > > > Please find attached the clk_summary for v6.12-rc2 before and > > > after the > > > reversion (the one after the reversion is 6.12- > > > rc2_summary_postfix). > > Thank you, this helped greatly. > > > > I believe I know why it used to kind-of work for you, but I'm > > afraid this used to work by sheer chance and it does not really > > work correctly for the panel you use, even if the panel likely does > > show the correct content. But, there is a way to make it work > > properly for the panel you use. > > > > First of all, the pixel clock never really matched the panel- > > simple.c pixel clock for the edt_etml1010g3dra_timing: > > > > $ grep '\<media_disp2_pix\>' 6.12-rc2_summary_postfix > > media_disp2_pix 1 1 0 74250000 ... > > ^^^^^^^^ > > > > $ grep -A 1 edt_etml1010g3dra_timing drivers/gpu/drm/panel/panel- > > simple.c > > static const struct display_timing edt_etml1010g3dra_timing = { > > .pixelclock = { 66300000, 72400000, 78900000 }, > > ^^^^^^^^ > > > > The pixel clock are within tolerance, but there is a discrepancy > > 74250000 != 72400000 . > > > > Since commit 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB > > nodes") the IMX8MP_VIDEO_PLL1_OUT is set to a very specific > > frequency of 1039500000 Hz, which tidily divides by 2 to 519750000 > > Hz (which is your LVDS serializer frequency) and divides by 7 to > > 74250000 Hz which is your LCDIF pixel clock. > > > > This Video PLL1 configuration since moved to &media_blk_ctrl {} , > > but it is still in the imx8mp.dtsi . Therefore, to make your panel > > work at the correct desired pixel clock frequency instead of some > > random one inherited from imx8mp.dtsi, add the following to the > > pollux DT, I believe that will fix the problem and is the correct > > fix: > > > > &media_blk_ctrl { > > // 506800000 = 72400000 * 7 (for single-link LVDS, this is > > enough) > > // there is no need to multiply the clock by * 2 > > assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, > > <500000000>, <506800000>; > > This assigns "video_pll1" clock rate to 506.8MHz which is currently > not > listed in imx_pll1443x_tbl[]. > > Does the below patch[1] fix the regression issue? It explicitly sets > the clock frequency of the panel timing to 74.25MHz. > > [1] > https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 > > > }; > > > > Can you please test whether this works and the pixel clock are > > accurate in /sys/kernel/debug/clk/clk_summary ? > > > > Now ... as for the LVDS serializer clock ... that is more > > complicated. > > > > The LCDIF driver does its .atomic_enable first , configures the > > pixel clock (and the Video PLL now) and enables the clock. The LVDS > > LDB serializer driver does its .atomic_enable second and cannot > > reconfigure the clock anymore, the Video PLL is stuck at /7 rate > > set by LCDIF driver and won't budge because the clock are already > > enabled. I'm currently trying to figure out if this can be improved > > somehow, but I believe that would be material for next release. > > > This patch also fixes the regression! Tested-by: Isaac Scott <isaac.scott@ideasonboard.com>
On Thu, 2024-10-10 at 16:54 +0100, Isaac Scott wrote: To be clear, my reply applies to the patch referenced by [1] Tested-by: Isaac Scott <isaac.scott@ideasonboard.com> > On Thu, 2024-10-10 at 13:31 +0800, Liu Ying wrote: > > On 10/09/2024, Marek Vasut wrote: > > > On 10/8/24 12:07 PM, Isaac Scott wrote: > > > > On Mon, 2024-10-07 at 20:06 +0200, Marek Vasut wrote: > > > > > On 10/7/24 7:01 PM, Isaac Scott wrote: > > > > > > Hi Marek, > > > > > > > > > > Hi, > > > > > > > > > > > On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote: > > > > > > > On 6/24/24 11:19 AM, Alexander Stein wrote: > > > > > > > > Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek > > > > > > > > Vasut: > > > > > > > > > In case an upstream bridge modified the required > > > > > > > > > clock > > > > > > > > > frequency > > > > > > > > > in its .atomic_check callback by setting > > > > > > > > > adjusted_mode.clock > > > > > > > > > , > > > > > > > > > make sure that clock frequency is generated by the > > > > > > > > > LCDIFv3 > > > > > > > > > block. > > > > > > > > > > > > > > > > > > This is useful e.g. when LCDIFv3 feeds DSIM which > > > > > > > > > feeds > > > > > > > > > TC358767 > > > > > > > > > with (e)DP output, where the TC358767 expects precise > > > > > > > > > timing > > > > > > > > > on > > > > > > > > > its input side, the precise timing must be generated > > > > > > > > > by > > > > > > > > > the > > > > > > > > > LCDIF. > > > > > > > > > > > > > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > > > > > > > > > > > > > > With the other rc358767 patches in place, this does the > > > > > > > > trick. > > > > > > > > Reviewed-by: Alexander Stein > > > > > > > > <alexander.stein@ew.tq-group.com> > > > > > > > > > > > > > > I'll pick this up next week if there is no objection. > > > > > > > > > > > > Unfortunately, this has caused a regression that is present > > > > > > in > > > > > > v6.12- > > > > > > rc1 on the i.MX8MP PHYTEC Pollux using the > > > > > > arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux- > > > > > > rdk.dts. > > > > > > The > > > > > > display is the edt,etml1010g3dra panel, as per the upstream > > > > > > dts. We > > > > > > bisected to this commit, and reverting this change fixed > > > > > > the > > > > > > screen. > > > > > > > > > > > > We then tried to retest this on top of v6.12-rc2, and found > > > > > > we also > > > > > > had > > > > > > to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 > > > > > > ("clk: > > > > > > imx: > > > > > > clk-imx8mp: Allow media_disp pixel clock reconfigure parent > > > > > > rate") > > > > > > alongside this. Reverting these two commits makes the > > > > > > display > > > > > > work > > > > > > again at -rc2. > > > > > > > > > > > > Do you have any suggestions on anything we might be missing > > > > > > on our > > > > > > end? > > > > > > Please let me know if there's anything you'd like me to > > > > > > test > > > > > > as I'm > > > > > > not > > > > > > sure what the underlying fault was here. > > > > > I believe what is going on is that the LCDIF cannot configure > > > > > its > > > > > upstream clock because something else is already using those > > > > > clock > > > > > and > > > > > it set those clock to a specific frequency. LCDIF is now > > > > > trying > > > > > to > > > > > configure those clock to match the LVDS panel, and it fails, > > > > > so > > > > > it > > > > > tries > > > > > to set some approximate clock and that is not good enough for > > > > > the > > > > > LVDS > > > > > panel. > > > > > > > > > > Can you share dump of /sys/kernel/debug/clk/clk_summary on > > > > > failing > > > > > and > > > > > working system ? You might see the difference around the > > > > > "video" > > > > > clock. > > > > > > > > > > (I have seen this behavior before, the fix was usually a > > > > > matter > > > > > of > > > > > moving one of the LCDIFs to another upstream clock like PLL3, > > > > > so it > > > > > can > > > > > pick well matching output clock instead of some horrid > > > > > approximation > > > > > which then drives the panel likely out of specification) > > > > > > > > Hi Marek, > > > > > > > > Please find attached the clk_summary for v6.12-rc2 before and > > > > after the > > > > reversion (the one after the reversion is 6.12- > > > > rc2_summary_postfix). > > > Thank you, this helped greatly. > > > > > > I believe I know why it used to kind-of work for you, but I'm > > > afraid this used to work by sheer chance and it does not really > > > work correctly for the panel you use, even if the panel likely > > > does > > > show the correct content. But, there is a way to make it work > > > properly for the panel you use. > > > > > > First of all, the pixel clock never really matched the panel- > > > simple.c pixel clock for the edt_etml1010g3dra_timing: > > > > > > $ grep '\<media_disp2_pix\>' 6.12-rc2_summary_postfix > > > media_disp2_pix 1 1 0 74250000 ... > > > ^^^^^^^^ > > > > > > $ grep -A 1 edt_etml1010g3dra_timing drivers/gpu/drm/panel/panel- > > > simple.c > > > static const struct display_timing edt_etml1010g3dra_timing = { > > > .pixelclock = { 66300000, 72400000, 78900000 }, > > > ^^^^^^^^ > > > > > > The pixel clock are within tolerance, but there is a discrepancy > > > 74250000 != 72400000 . > > > > > > Since commit 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB > > > nodes") the IMX8MP_VIDEO_PLL1_OUT is set to a very specific > > > frequency of 1039500000 Hz, which tidily divides by 2 to > > > 519750000 > > > Hz (which is your LVDS serializer frequency) and divides by 7 to > > > 74250000 Hz which is your LCDIF pixel clock. > > > > > > This Video PLL1 configuration since moved to &media_blk_ctrl {} , > > > but it is still in the imx8mp.dtsi . Therefore, to make your > > > panel > > > work at the correct desired pixel clock frequency instead of some > > > random one inherited from imx8mp.dtsi, add the following to the > > > pollux DT, I believe that will fix the problem and is the correct > > > fix: > > > > > > &media_blk_ctrl { > > > // 506800000 = 72400000 * 7 (for single-link LVDS, this is > > > enough) > > > // there is no need to multiply the clock by * 2 > > > assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, > > > <500000000>, <506800000>; > > > > This assigns "video_pll1" clock rate to 506.8MHz which is currently > > not > > listed in imx_pll1443x_tbl[]. > > > > Does the below patch[1] fix the regression issue? It explicitly > > sets > > the clock frequency of the panel timing to 74.25MHz. > > > > [1] > > https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 > > > > > }; > > > > > > Can you please test whether this works and the pixel clock are > > > accurate in /sys/kernel/debug/clk/clk_summary ? > > > > > > Now ... as for the LVDS serializer clock ... that is more > > > complicated. > > > > > > The LCDIF driver does its .atomic_enable first , configures the > > > pixel clock (and the Video PLL now) and enables the clock. The > > > LVDS > > > LDB serializer driver does its .atomic_enable second and cannot > > > reconfigure the clock anymore, the Video PLL is stuck at /7 rate > > > set by LCDIF driver and won't budge because the clock are already > > > enabled. I'm currently trying to figure out if this can be > > > improved > > > somehow, but I believe that would be material for next release. > > > > > > > This patch also fixes the regression! > Tested-by: Isaac Scott <isaac.scott@ideasonboard.com>
On 10/10/24 7:31 AM, Liu Ying wrote: Hi, >> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: >> >> &media_blk_ctrl { >> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) >> // there is no need to multiply the clock by * 2 >> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; > > This assigns "video_pll1" clock rate to 506.8MHz which is currently not > listed in imx_pll1443x_tbl[]. Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. > Does the below patch[1] fix the regression issue? It explicitly sets > the clock frequency of the panel timing to 74.25MHz. > > [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. [...]
On 10/11/2024, Marek Vasut wrote: > On 10/10/24 7:31 AM, Liu Ying wrote: > > Hi, Hi, > >>> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: >>> >>> &media_blk_ctrl { >>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) >>> // there is no need to multiply the clock by * 2 >>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; >> >> This assigns "video_pll1" clock rate to 506.8MHz which is currently not >> listed in imx_pll1443x_tbl[]. > > Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. Ack. > >> Does the below patch[1] fix the regression issue? It explicitly sets >> the clock frequency of the panel timing to 74.25MHz. >> >> [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 > That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. At least the patch[1] is legitimate now to override the display timing of the panel because the override mode is something panel-simple.c supports. And, pixel clock @74.25MHz is not out of the panel specification since edt_etml1010g3dra_timing indicates the minimum as 66.3MHz and the maximum as 78.9MHz. Furthermore, if "PHYTEC phyBOARD-Pollux i.MX8MP" also supports something like MIPI DSI to HDMI, then 74.25MHz panel pixel clock rate is more desirable because the LVDS display and the MIPI DSI display pipeline with typical 148.5MHz/74.25MHz pixel clock rates may use one single "video_pll1" clock. Anyway, I think it is ok to use the patch[1] or assigning "video_pll1" clock rate to 506.8MHz in DT(no things like MIPI DSI to HDMI in existing DT). > > [...]
On 10/11/24 5:10 AM, Liu Ying wrote: Hi, >>>> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: >>>> >>>> &media_blk_ctrl { >>>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) >>>> // there is no need to multiply the clock by * 2 >>>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; >>> >>> This assigns "video_pll1" clock rate to 506.8MHz which is currently not >>> listed in imx_pll1443x_tbl[]. >> >> Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. > > Ack. > >> >>> Does the below patch[1] fix the regression issue? It explicitly sets >>> the clock frequency of the panel timing to 74.25MHz. >>> >>> [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 >> That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. > > At least the patch[1] is legitimate now to override the display > timing of the panel because the override mode is something > panel-simple.c supports. It may be possible to override the mode, but why would this be the desired if the panel-simple.c already contains valid accurate timings for this particular panel ? > And, pixel clock @74.25MHz is not out > of the panel specification since edt_etml1010g3dra_timing > indicates the minimum as 66.3MHz and the maximum as 78.9MHz. The panel-simple.c already contains timings for this panel, which are accurate and follow the panel datasheet. If the goal here is to support approximate panel timings between the currently available three options (min/typ/max) listed in panel-simple, then that is another discussion for another patch. > Furthermore, if "PHYTEC phyBOARD-Pollux i.MX8MP" also supports > something like MIPI DSI to HDMI, then 74.25MHz panel pixel clock > rate is more desirable because the LVDS display and the MIPI DSI > display pipeline with typical 148.5MHz/74.25MHz pixel clock rates > may use one single "video_pll1" clock. I actually do have exactly this use case on one system -- one LVDS panel and one MIPI DSI panel -- the solution is really easy, source the LVDS pixel clock from Video PLL and the DSI clock from e.g. PLL3 . > Anyway, I think it is ok to use the patch[1] or assigning > "video_pll1" clock rate to 506.8MHz in DT(no things like MIPI > DSI to HDMI in existing DT). I believe for the current release, it is better to update the Video PLL clock in this one board DT, because that is minimum impact change isolated to this board and fixes a real issue where the LVDS panel worked within specification only by sheer chance.
Quoting Marek Vasut (2024-10-12 21:37:59) > On 10/11/24 5:10 AM, Liu Ying wrote: > > Hi, > > >>>> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: > >>>> > >>>> &media_blk_ctrl { > >>>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) > >>>> // there is no need to multiply the clock by * 2 > >>>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; > >>> > >>> This assigns "video_pll1" clock rate to 506.8MHz which is currently not > >>> listed in imx_pll1443x_tbl[]. > >> > >> Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. > > > > Ack. > > > >> > >>> Does the below patch[1] fix the regression issue? It explicitly sets > >>> the clock frequency of the panel timing to 74.25MHz. > >>> > >>> [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 > >> That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. > > > > At least the patch[1] is legitimate now to override the display > > timing of the panel because the override mode is something > > panel-simple.c supports. > > It may be possible to override the mode, but why would this be the > desired if the panel-simple.c already contains valid accurate timings > for this particular panel ? I'm confused a little here. Why is it that setting the panel timings in the DT as per [1] make the display work, while the panel timeings in panel-simple alone are not enough? Is there some difference in code path for 'how' the panel timings are set as to whether they will apply fully or not ? -- Kieran > > > And, pixel clock @74.25MHz is not out > > of the panel specification since edt_etml1010g3dra_timing > > indicates the minimum as 66.3MHz and the maximum as 78.9MHz. > > The panel-simple.c already contains timings for this panel, which are > accurate and follow the panel datasheet. If the goal here is to support > approximate panel timings between the currently available three options > (min/typ/max) listed in panel-simple, then that is another discussion > for another patch. > > > Furthermore, if "PHYTEC phyBOARD-Pollux i.MX8MP" also supports > > something like MIPI DSI to HDMI, then 74.25MHz panel pixel clock > > rate is more desirable because the LVDS display and the MIPI DSI > > display pipeline with typical 148.5MHz/74.25MHz pixel clock rates > > may use one single "video_pll1" clock. > > I actually do have exactly this use case on one system -- one LVDS panel > and one MIPI DSI panel -- the solution is really easy, source the LVDS > pixel clock from Video PLL and the DSI clock from e.g. PLL3 . > > > Anyway, I think it is ok to use the patch[1] or assigning > > "video_pll1" clock rate to 506.8MHz in DT(no things like MIPI > > DSI to HDMI in existing DT). > I believe for the current release, it is better to update the Video PLL > clock in this one board DT, because that is minimum impact change > isolated to this board and fixes a real issue where the LVDS panel > worked within specification only by sheer chance.
On 10/19/24 11:49 PM, Kieran Bingham wrote: > Quoting Marek Vasut (2024-10-12 21:37:59) >> On 10/11/24 5:10 AM, Liu Ying wrote: >> >> Hi, >> >>>>>> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: >>>>>> >>>>>> &media_blk_ctrl { >>>>>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) >>>>>> // there is no need to multiply the clock by * 2 >>>>>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; >>>>> >>>>> This assigns "video_pll1" clock rate to 506.8MHz which is currently not >>>>> listed in imx_pll1443x_tbl[]. >>>> >>>> Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. >>> >>> Ack. >>> >>>> >>>>> Does the below patch[1] fix the regression issue? It explicitly sets >>>>> the clock frequency of the panel timing to 74.25MHz. >>>>> >>>>> [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 >>>> That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. >>> >>> At least the patch[1] is legitimate now to override the display >>> timing of the panel because the override mode is something >>> panel-simple.c supports. >> >> It may be possible to override the mode, but why would this be the >> desired if the panel-simple.c already contains valid accurate timings >> for this particular panel ? > > I'm confused a little here. Why is it that setting the panel timings in > the DT as per [1] make the display work, while the panel timeings in > panel-simple alone are not enough? > > Is there some difference in code path for 'how' the panel timings are > set as to whether they will apply fully or not ? Because [1] sets inaccurate pixel clock of 74.25 MHz, which can be divided down from random default Video PLL setting of 1039.5 MHz set in imx8mp.dtsi media_blk_ctrl , 1039.5 / 74.25 = 14 . The panel-simple pixel clock are 72.4 MHz, to achieve that accurately, it is necessary to reconfigure the Video PLL frequency to 506.8 MHz , which LCDIFv3 can do, but LDB can not, hence it has to be done in DT for now.
Quoting Marek Vasut (2024-10-20 03:49:29) > On 10/19/24 11:49 PM, Kieran Bingham wrote: > > Quoting Marek Vasut (2024-10-12 21:37:59) > >> On 10/11/24 5:10 AM, Liu Ying wrote: > >> > >> Hi, > >> > >>>>>> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: > >>>>>> > >>>>>> &media_blk_ctrl { > >>>>>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) > >>>>>> // there is no need to multiply the clock by * 2 > >>>>>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; > >>>>> > >>>>> This assigns "video_pll1" clock rate to 506.8MHz which is currently not > >>>>> listed in imx_pll1443x_tbl[]. > >>>> > >>>> Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. > >>> > >>> Ack. > >>> > >>>> > >>>>> Does the below patch[1] fix the regression issue? It explicitly sets > >>>>> the clock frequency of the panel timing to 74.25MHz. > >>>>> > >>>>> [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 > >>>> That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. > >>> > >>> At least the patch[1] is legitimate now to override the display > >>> timing of the panel because the override mode is something > >>> panel-simple.c supports. > >> > >> It may be possible to override the mode, but why would this be the > >> desired if the panel-simple.c already contains valid accurate timings > >> for this particular panel ? > > > > I'm confused a little here. Why is it that setting the panel timings in > > the DT as per [1] make the display work, while the panel timeings in > > panel-simple alone are not enough? > > > > Is there some difference in code path for 'how' the panel timings are > > set as to whether they will apply fully or not ? > Because [1] sets inaccurate pixel clock of 74.25 MHz, which can be > divided down from random default Video PLL setting of 1039.5 MHz set in > imx8mp.dtsi media_blk_ctrl , 1039.5 / 74.25 = 14 . > > The panel-simple pixel clock are 72.4 MHz, to achieve that accurately, > it is necessary to reconfigure the Video PLL frequency to 506.8 MHz , > which LCDIFv3 can do, but LDB can not, hence it has to be done in DT for > now. Aha - right - Thanks, I'd missed the part that 74.25 MHz /is not/ the correct or supported pixel clock for the panel, so it just becomes 'close enough' and lucky that it works... Now I understand how your proposed : > >>>>>> &media_blk_ctrl { > >>>>>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) > >>>>>> // there is no need to multiply the clock by * 2 > >>>>>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; > >>>>> > >>>>> This assigns "video_pll1" clock rate to 506.8MHz which is currently not > >>>>> listed in imx_pll1443x_tbl[]. is more accurate. But is that acceptable for DT ? To just hardcode clocks like that? Or is this something we'll then remove when the additional patches make it upstream? (I'm curious on the basis that I thought we treat DT as 'firmware' so if we put this in we expect it to be there forever?) All of this seems like perhaps it should be in an overlay for the display too - but given this board comes with this panel as a kit - I suspect it's fine to keep it all there. -- Kieran
On Sun, Oct 20, 2024 at 04:49:29AM +0200, Marek Vasut wrote: > On 10/19/24 11:49 PM, Kieran Bingham wrote: > > Quoting Marek Vasut (2024-10-12 21:37:59) > > > On 10/11/24 5:10 AM, Liu Ying wrote: > > > > > > Hi, > > > > > > > > > > This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: > > > > > > > > > > > > > > &media_blk_ctrl { > > > > > > > // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) > > > > > > > // there is no need to multiply the clock by * 2 > > > > > > > assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; > > > > > > > > > > > > This assigns "video_pll1" clock rate to 506.8MHz which is currently not > > > > > > listed in imx_pll1443x_tbl[]. > > > > > > > > > > Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. > > > > > > > > Ack. > > > > > > > > > > > > > > > Does the below patch[1] fix the regression issue? It explicitly sets > > > > > > the clock frequency of the panel timing to 74.25MHz. > > > > > > > > > > > > [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 > > > > > That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. > > > > > > > > At least the patch[1] is legitimate now to override the display > > > > timing of the panel because the override mode is something > > > > panel-simple.c supports. > > > > > > It may be possible to override the mode, but why would this be the > > > desired if the panel-simple.c already contains valid accurate timings > > > for this particular panel ? > > > > I'm confused a little here. Why is it that setting the panel timings in > > the DT as per [1] make the display work, while the panel timeings in > > panel-simple alone are not enough? > > > > Is there some difference in code path for 'how' the panel timings are > > set as to whether they will apply fully or not ? > Because [1] sets inaccurate pixel clock of 74.25 MHz, which can be divided > down from random default Video PLL setting of 1039.5 MHz set in imx8mp.dtsi > media_blk_ctrl , 1039.5 / 74.25 = 14 . > > The panel-simple pixel clock are 72.4 MHz, to achieve that accurately, it is > necessary to reconfigure the Video PLL frequency to 506.8 MHz , which > LCDIFv3 can do, but LDB can not, hence it has to be done in DT for now. That the clock driver is broken and thus should be fixed through the DT is a bit backward, don't you think? AFAIU, the clock can't reach the ideal pixel clock panel-simple has. Do you have the datasheet for that panel? If so, using display_timings and shortening/extending the blanking timings to match the clock that can be provided seems like a more robust solution. Maxime
On 10/21/24 1:10 PM, Kieran Bingham wrote: > Quoting Marek Vasut (2024-10-20 03:49:29) >> On 10/19/24 11:49 PM, Kieran Bingham wrote: >>> Quoting Marek Vasut (2024-10-12 21:37:59) >>>> On 10/11/24 5:10 AM, Liu Ying wrote: >>>> >>>> Hi, >>>> >>>>>>>> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: >>>>>>>> >>>>>>>> &media_blk_ctrl { >>>>>>>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) >>>>>>>> // there is no need to multiply the clock by * 2 >>>>>>>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; >>>>>>> >>>>>>> This assigns "video_pll1" clock rate to 506.8MHz which is currently not >>>>>>> listed in imx_pll1443x_tbl[]. >>>>>> >>>>>> Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. >>>>> >>>>> Ack. >>>>> >>>>>> >>>>>>> Does the below patch[1] fix the regression issue? It explicitly sets >>>>>>> the clock frequency of the panel timing to 74.25MHz. >>>>>>> >>>>>>> [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 >>>>>> That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. >>>>> >>>>> At least the patch[1] is legitimate now to override the display >>>>> timing of the panel because the override mode is something >>>>> panel-simple.c supports. >>>> >>>> It may be possible to override the mode, but why would this be the >>>> desired if the panel-simple.c already contains valid accurate timings >>>> for this particular panel ? >>> >>> I'm confused a little here. Why is it that setting the panel timings in >>> the DT as per [1] make the display work, while the panel timeings in >>> panel-simple alone are not enough? >>> >>> Is there some difference in code path for 'how' the panel timings are >>> set as to whether they will apply fully or not ? >> Because [1] sets inaccurate pixel clock of 74.25 MHz, which can be >> divided down from random default Video PLL setting of 1039.5 MHz set in >> imx8mp.dtsi media_blk_ctrl , 1039.5 / 74.25 = 14 . >> >> The panel-simple pixel clock are 72.4 MHz, to achieve that accurately, >> it is necessary to reconfigure the Video PLL frequency to 506.8 MHz , >> which LCDIFv3 can do, but LDB can not, hence it has to be done in DT for >> now. > > Aha - right - Thanks, I'd missed the part that 74.25 MHz /is not/ the > correct or supported pixel clock for the panel It is inaccurate, it is still within the spec ... > , so it just becomes > 'close enough' and lucky that it works... ... but only by sheer chance, because the Video PLL in imx8mp.dtsi is accidentally set to frequency that is just close enough to be divisible to the inaccurate 74.25 MHz . > Now I understand how your proposed : > >>>>>>>> &media_blk_ctrl { >>>>>>>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) >>>>>>>> // there is no need to multiply the clock by * 2 >>>>>>>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; >>>>>>> >>>>>>> This assigns "video_pll1" clock rate to 506.8MHz which is currently not >>>>>>> listed in imx_pll1443x_tbl[]. > > is more accurate. But is that acceptable for DT ? To just hardcode > clocks like that? I am not happy about it, but it is the best we can do right now. See these two patches, they might address that part for next cycle: clk: imx: clk-imx8mp: Allow LDB serializer clock reconfigure parent rate drm: bridge: ldb: Configure LDB clock in .mode_set > Or is this something we'll then remove when the additional patches make > it upstream? (I'm curious on the basis that I thought we treat DT as > 'firmware' so if we put this in we expect it to be there forever?) It is already there in imx8mp.dtsi , so we are not making the situation any worse, rather the opposite. > All of this seems like perhaps it should be in an overlay for the > display too - but given this board comes with this panel as a kit - I > suspect it's fine to keep it all there. That's a separate topic, but yes, DTOs for displays are a good thing to have.
On 10/21/24 1:48 PM, Maxime Ripard wrote: > On Sun, Oct 20, 2024 at 04:49:29AM +0200, Marek Vasut wrote: >> On 10/19/24 11:49 PM, Kieran Bingham wrote: >>> Quoting Marek Vasut (2024-10-12 21:37:59) >>>> On 10/11/24 5:10 AM, Liu Ying wrote: >>>> >>>> Hi, >>>> >>>>>>>> This Video PLL1 configuration since moved to &media_blk_ctrl {} , but it is still in the imx8mp.dtsi . Therefore, to make your panel work at the correct desired pixel clock frequency instead of some random one inherited from imx8mp.dtsi, add the following to the pollux DT, I believe that will fix the problem and is the correct fix: >>>>>>>> >>>>>>>> &media_blk_ctrl { >>>>>>>> // 506800000 = 72400000 * 7 (for single-link LVDS, this is enough) >>>>>>>> // there is no need to multiply the clock by * 2 >>>>>>>> assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <500000000>, <506800000>; >>>>>>> >>>>>>> This assigns "video_pll1" clock rate to 506.8MHz which is currently not >>>>>>> listed in imx_pll1443x_tbl[]. >>>>>> >>>>>> Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") the 1443x PLLs can be configured to arbitrary rates which for video PLL is desirable as those should produce accurate clock. >>>>> >>>>> Ack. >>>>> >>>>>> >>>>>>> Does the below patch[1] fix the regression issue? It explicitly sets >>>>>>> the clock frequency of the panel timing to 74.25MHz. >>>>>>> >>>>>>> [1] https://patchwork.freedesktop.org/patch/616905/?series=139266&rev=1 >>>>>> That patch is wrong, there is an existing entry for this panel in panel-simple.c which is correct and precise, please do not add that kind of imprecise duplicate timings into DT. >>>>> >>>>> At least the patch[1] is legitimate now to override the display >>>>> timing of the panel because the override mode is something >>>>> panel-simple.c supports. >>>> >>>> It may be possible to override the mode, but why would this be the >>>> desired if the panel-simple.c already contains valid accurate timings >>>> for this particular panel ? >>> >>> I'm confused a little here. Why is it that setting the panel timings in >>> the DT as per [1] make the display work, while the panel timeings in >>> panel-simple alone are not enough? >>> >>> Is there some difference in code path for 'how' the panel timings are >>> set as to whether they will apply fully or not ? >> Because [1] sets inaccurate pixel clock of 74.25 MHz, which can be divided >> down from random default Video PLL setting of 1039.5 MHz set in imx8mp.dtsi >> media_blk_ctrl , 1039.5 / 74.25 = 14 . >> >> The panel-simple pixel clock are 72.4 MHz, to achieve that accurately, it is >> necessary to reconfigure the Video PLL frequency to 506.8 MHz , which >> LCDIFv3 can do, but LDB can not, hence it has to be done in DT for now. > > That the clock driver is broken and thus should be fixed through the DT is a > bit backward, don't you think? See these two patches, they might address that part for next cycle: clk: imx: clk-imx8mp: Allow LDB serializer clock reconfigure parent rate drm: bridge: ldb: Configure LDB clock in .mode_set For this cycle, fixing up the frequency that is already incorrectly set in imx8mp.dtsi in board DT is the least impact approach, see arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1 frequency to 506.8 MHz > AFAIU, the clock can't reach the ideal pixel clock panel-simple has. Do > you have the datasheet for that panel? No > If so, using display_timings and shortening/extending the blanking > timings to match the clock that can be provided seems like a more robust > solution. The PLL has to be configured correctly, see the two patches listed above.
diff --git a/drivers/gpu/drm/mxsfb/lcdif_kms.c b/drivers/gpu/drm/mxsfb/lcdif_kms.c index 2541d2de4e45f..dbd42cc1da87f 100644 --- a/drivers/gpu/drm/mxsfb/lcdif_kms.c +++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c @@ -407,8 +407,7 @@ static void lcdif_crtc_mode_set_nofb(struct drm_crtc_state *crtc_state, struct drm_display_mode *m = &crtc_state->adjusted_mode; DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n", - m->crtc_clock, - (int)(clk_get_rate(lcdif->clk) / 1000)); + m->clock, (int)(clk_get_rate(lcdif->clk) / 1000)); DRM_DEV_DEBUG_DRIVER(drm->dev, "Bridge bus_flags: 0x%08X\n", lcdif_crtc_state->bus_flags); DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); @@ -538,7 +537,7 @@ static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_device *drm = lcdif->drm; dma_addr_t paddr; - clk_set_rate(lcdif->clk, m->crtc_clock * 1000); + clk_set_rate(lcdif->clk, m->clock * 1000); pm_runtime_get_sync(drm->dev);
In case an upstream bridge modified the required clock frequency in its .atomic_check callback by setting adjusted_mode.clock , make sure that clock frequency is generated by the LCDIFv3 block. This is useful e.g. when LCDIFv3 feeds DSIM which feeds TC358767 with (e)DP output, where the TC358767 expects precise timing on its input side, the precise timing must be generated by the LCDIF. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Daniel Vetter <daniel@ffwll.ch> Cc: David Airlie <airlied@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Lukas F. Hartmann <lukas@mntmn.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Stefan Agner <stefan@agner.ch> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org --- drivers/gpu/drm/mxsfb/lcdif_kms.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)