| Message ID | 20241011104142.1181773-7-quic_qianyu@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Fri, Oct 11, 2024 at 03:41:40AM -0700, Qiang Yu wrote: > On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence > they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by > introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping > won't be configured during init. > > Fixes: d1997c987814 ("PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p") > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Fri, Oct 11, 2024 at 03:41:40AM -0700, Qiang Yu wrote: > On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence > they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by > introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping '...namely ops_1_21_0 which is same as ops_1_9_0 without config_sid() callback' > won't be configured during init. > > Fixes: d1997c987814 ("PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p") > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 88a98be930e3..468bd4242e61 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > }; > > +/* Qcom IP rev.: 1.21.0 */ > +static const struct qcom_pcie_ops ops_1_21_0 = { > + .get_resources = qcom_pcie_get_resources_2_7_0, > + .init = qcom_pcie_init_2_7_0, > + .post_init = qcom_pcie_post_init_2_7_0, > + .host_post_init = qcom_pcie_host_post_init_2_7_0, > + .deinit = qcom_pcie_deinit_2_7_0, > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > +}; > + > static const struct qcom_pcie_cfg cfg_1_0_0 = { > .ops = &ops_1_0_0, > }; > @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { > }; > > static const struct qcom_pcie_cfg cfg_sc8280xp = { > - .ops = &ops_1_9_0, > + .ops = &ops_1_21_0, > .no_l0s = true, > }; > > -- > 2.34.1 >
[+cc Johan; if you tag a commit with Fixes:, please cc the author of that commit!] On Fri, Oct 11, 2024 at 03:41:40AM -0700, Qiang Yu wrote: > On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence > they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by > introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping > won't be configured during init. Can you make the subject line say something specific about what this patch does? "Fix the ops" really doesn't include any useful information. Based on the Fixes: below, this has to do with ASPM, so the subject line (and the commit log) should probably say something about ASPM. I don't see the connection between your mention of SMMUv3 and ASPM. Are there two logical changes here that should be two separate patches? > Fixes: d1997c987814 ("PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p") > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 88a98be930e3..468bd4242e61 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > }; > > +/* Qcom IP rev.: 1.21.0 */ > +static const struct qcom_pcie_ops ops_1_21_0 = { > + .get_resources = qcom_pcie_get_resources_2_7_0, > + .init = qcom_pcie_init_2_7_0, > + .post_init = qcom_pcie_post_init_2_7_0, > + .host_post_init = qcom_pcie_host_post_init_2_7_0, > + .deinit = qcom_pcie_deinit_2_7_0, > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > +}; > + > static const struct qcom_pcie_cfg cfg_1_0_0 = { > .ops = &ops_1_0_0, > }; > @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { > }; > > static const struct qcom_pcie_cfg cfg_sc8280xp = { > - .ops = &ops_1_9_0, > + .ops = &ops_1_21_0, > .no_l0s = true, > }; > > -- > 2.34.1 >
On 10/15/2024 1:18 AM, Bjorn Helgaas wrote: > [+cc Johan; if you tag a commit with Fixes:, please cc the author of > that commit!] > > On Fri, Oct 11, 2024 at 03:41:40AM -0700, Qiang Yu wrote: >> On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence >> they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by >> introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping >> won't be configured during init. > Can you make the subject line say something specific about what this > patch does? "Fix the ops" really doesn't include any useful > information. Sure, will directly say Remove BDF2SID mapping config for SC8280XP in subject. > > Based on the Fixes: below, this has to do with ASPM, so the subject > line (and the commit log) should probably say something about ASPM. > > I don't see the connection between your mention of SMMUv3 and ASPM. > Are there two logical changes here that should be two separate > patches? This patch is to remove config_sid callback for sc8280x as it supports SMMUv3. This patch is not related to ASPM. Look like using 70574511f3f ("PCI: qcom: Add support for SC8280XP") in Fixes tag is better. Sorry for the confusion. Thanks, Qiang >> Fixes: d1997c987814 ("PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p") >> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- >> 1 file changed, 11 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 88a98be930e3..468bd4242e61 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { >> .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, >> }; >> >> +/* Qcom IP rev.: 1.21.0 */ >> +static const struct qcom_pcie_ops ops_1_21_0 = { >> + .get_resources = qcom_pcie_get_resources_2_7_0, >> + .init = qcom_pcie_init_2_7_0, >> + .post_init = qcom_pcie_post_init_2_7_0, >> + .host_post_init = qcom_pcie_host_post_init_2_7_0, >> + .deinit = qcom_pcie_deinit_2_7_0, >> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, >> +}; >> + >> static const struct qcom_pcie_cfg cfg_1_0_0 = { >> .ops = &ops_1_0_0, >> }; >> @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { >> }; >> >> static const struct qcom_pcie_cfg cfg_sc8280xp = { >> - .ops = &ops_1_9_0, >> + .ops = &ops_1_21_0, >> .no_l0s = true, >> }; >> >> -- >> 2.34.1 >>
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 88a98be930e3..468bd4242e61 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; +/* Qcom IP rev.: 1.21.0 */ +static const struct qcom_pcie_ops ops_1_21_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .post_init = qcom_pcie_post_init_2_7_0, + .host_post_init = qcom_pcie_host_post_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 = { .ops = &ops_1_0_0, }; @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { }; static const struct qcom_pcie_cfg cfg_sc8280xp = { - .ops = &ops_1_9_0, + .ops = &ops_1_21_0, .no_l0s = true, };
On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping won't be configured during init. Fixes: d1997c987814 ("PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p") Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)