[v3] clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set

Commit Message

Barnabás Czémán Oct. 6, 2024, 8:51 p.m. UTC

Many qcom clock drivers do not have .width set. In that case value of
(p)->width - 1 will be negative which breaks clock tree. Fix this
by checking if width is zero, and pass 3 to GENMASK if that's the case.

Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
Signed-off-by: Barnabás Czémán <[e-mail]>
---
Changes in v3:
- Remove one of the fixes tag.
- Link to v2: https://lore.kernel.org/r/[e-mail]

Changes in v2:
- Pass 3 to GENMASK instead of 0.
- Add more Fixes tag for reference root cause.
- Link to v1: https://lore.kernel.org/r/[e-mail]
---
 drivers/clk/qcom/clk-alpha-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


---
base-commit: 58ca61c1a866bfdaa5e19fb19a2416764f847d75
change-id: 20240925-fix-postdiv-mask-ba47ecd23ea3

Best regards,

Comments

Dmitry Baryshkov Oct. 6, 2024, 9:03 p.m. UTC | #1

On Sun, Oct 06, 2024 at 10:51:58PM GMT, Barnabás Czémán wrote:
> Many qcom clock drivers do not have .width set. In that case value of
> (p)->width - 1 will be negative which breaks clock tree. Fix this
> by checking if width is zero, and pass 3 to GENMASK if that's the case.
> 
> Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
> Signed-off-by: Barnabás Czémán <[e-mail]>
> ---
> Changes in v3:
> - Remove one of the fixes tag.
> - Link to v2: https://lore.kernel.org/r/[e-mail]
> 
> Changes in v2:
> - Pass 3 to GENMASK instead of 0.
> - Add more Fixes tag for reference root cause.
> - Link to v1: https://lore.kernel.org/r/[e-mail]
> ---
>  drivers/clk/qcom/clk-alpha-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Dmitry Baryshkov <[e-mail]>

Christopher Obbard Oct. 11, 2024, 9:28 a.m. UTC | #2

On Sun, 6 Oct 2024 at 21:52, Barnabás Czémán
<[e-mail]> wrote:
> Many qcom clock drivers do not have .width set. In that case value of
> (p)->width - 1 will be negative which breaks clock tree. Fix this
> by checking if width is zero, and pass 3 to GENMASK if that's the case.
>
> Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
> Signed-off-by: Barnabás Czémán <[e-mail]>
> ---
> Changes in v3:
> - Remove one of the fixes tag.
> - Link to v2: https://lore.kernel.org/r/[e-mail]
>
> Changes in v2:
> - Pass 3 to GENMASK instead of 0.
> - Add more Fixes tag for reference root cause.
> - Link to v1: https://lore.kernel.org/r/[e-mail]
> ---
>  drivers/clk/qcom/clk-alpha-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Hi Barnabás,

This patch fixes a regression with UFS devfreq on msm8996 (introduced
with the linked commit in your patch) so:

Reviewed-by: Christopher Obbard <[e-mail]>
Tested-by: Christopher Obbard <[e-mail]>

Bjorn Andersson Oct. 16, 2024, 8:42 p.m. UTC | #3

On Sun, 06 Oct 2024 22:51:58 +0200, Barnabás Czémán wrote:
> Many qcom clock drivers do not have .width set. In that case value of
> (p)->width - 1 will be negative which breaks clock tree. Fix this
> by checking if width is zero, and pass 3 to GENMASK if that's the case.
> 
> 

Applied, thanks!

[1/1] clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set
      commit: e02bfea4d7ef587bb285ad5825da4e1973ac8263

Best regards,

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index f9105443d7dbb104e3cb091e59f43df25999f8b3..be9bee6ab65f6e08d5ae764d94a92e395e227fbc 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -40,7 +40,7 @@ 
 
 #define PLL_USER_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
 # define PLL_POST_DIV_SHIFT	8
-# define PLL_POST_DIV_MASK(p)	GENMASK((p)->width - 1, 0)
+# define PLL_POST_DIV_MASK(p)	GENMASK((p)->width ? (p)->width - 1 : 3, 0)
 # define PLL_ALPHA_MSB		BIT(15)
 # define PLL_ALPHA_EN		BIT(24)
 # define PLL_ALPHA_MODE		BIT(25)