| Message ID | 20240927142108.1156362-1-dave.jiang@intel.com |
|---|---|
| Headers | show |
| Series | acpi/hmat / cxl: Add exclusive caching enumeration and RAS support | expand |
On Fri, 27 Sep 2024 07:16:52 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > Hi all, > I'm looking for comments on the approach and the implementation of dealing with > this exclusive caching configuration. I have concerns with the discovering and > handling of I/O hole in the memory mapping and looking for suggestions on if > there are better ways to do it. I will be taking a 4 weeks sabbatical starting > next week and I apologize in advance in the delay on responses. Thank you in > advance for reviewing the patches. > > The MCE folks will be interested in patch 6/6 where MCE_PRIO_CXL is added. > > > Certain systems provide an exclusive caching memory configurations where a > 1:1 layout of DRAM and far memory (FR) such as CXL memory is utilized. In (FM) at least that is what you use later. > this configuration, the memory region is provided as a single memory region > to the OS. For example such as below: > > 128GB DRAM 128GB CXL memory > |------------------------------------|------------------------------------| So this differs slightly from what I expected. The ACPI spec change I believe allows for the CXL memory to be be N times bigger than the cache. I'm not against only supporting 1:1, but I didn't immediately see code to check for that and scream if it sees something different. Also as I mention in one of the patches, I don't recall the ACPI stuff giving an 'order' to the two types of memory. Maybe I'm missing that but in theory at least I think the code needs to be more flexible (or renamed perhaps). Jonathan
On 10/17/24 9:46 AM, Jonathan Cameron wrote: > On Fri, 27 Sep 2024 07:16:52 -0700 > Dave Jiang <dave.jiang@intel.com> wrote: > >> Hi all, >> I'm looking for comments on the approach and the implementation of dealing with >> this exclusive caching configuration. I have concerns with the discovering and >> handling of I/O hole in the memory mapping and looking for suggestions on if >> there are better ways to do it. I will be taking a 4 weeks sabbatical starting >> next week and I apologize in advance in the delay on responses. Thank you in >> advance for reviewing the patches. >> >> The MCE folks will be interested in patch 6/6 where MCE_PRIO_CXL is added. >> >> >> Certain systems provide an exclusive caching memory configurations where a >> 1:1 layout of DRAM and far memory (FR) such as CXL memory is utilized. In > (FM) at least that is what you use later. > > >> this configuration, the memory region is provided as a single memory region >> to the OS. For example such as below: >> >> 128GB DRAM 128GB CXL memory >> |------------------------------------|------------------------------------| > > So this differs slightly from what I expected. > The ACPI spec change I believe allows for the CXL memory to be be N times > bigger than the cache. Right. Spec allows that. Implementation I'm dealing with is only 1:1. So only limited implementation for now. > > I'm not against only supporting 1:1, but I didn't immediately see code > to check for that and scream if it sees something different. Yes. I need to add detection for that and emit warning. > > Also as I mention in one of the patches, I don't recall the ACPI stuff > giving an 'order' to the two types of memory. Maybe I'm missing that > but in theory at least I think the code needs to be more flexible > (or renamed perhaps). Yes no requirement by the spec on the ordering. Just available implementation. > > Jonathan > > >
Hi all, I'm looking for comments on the approach and the implementation of dealing with this exclusive caching configuration. I have concerns with the discovering and handling of I/O hole in the memory mapping and looking for suggestions on if there are better ways to do it. I will be taking a 4 weeks sabbatical starting next week and I apologize in advance in the delay on responses. Thank you in advance for reviewing the patches. The MCE folks will be interested in patch 6/6 where MCE_PRIO_CXL is added. Certain systems provide an exclusive caching memory configurations where a 1:1 layout of DRAM and far memory (FR) such as CXL memory is utilized. In this configuration, the memory region is provided as a single memory region to the OS. For example such as below: 128GB DRAM 128GB CXL memory |------------------------------------|------------------------------------| The kernel sees the region as a 256G system memory region. Data can reside in either DRAM or FM with no replication. Hot data is swapped into DRAM by the hardware behind the scenes. This kernel series introduces code to enumerate the side cache by the kernel when configured in a exclusive-cache configuration. It also adds RAS support to deal with the aliased memory addresses. A new ECN [1] to ACPI HMAT table was introduced and was approved to describe the "extended-linear" addressing for direct-mapped memory-side caches. A reserved field in the Memory Side Cache Information Structure of HMAT is redefined as "Address Mode" where a value of 1 is defined as Extended-linear mode. This value is valid if the cache is direct mapped. "It indicates that the associated address range (SRAT.MemoryAffinityStructure.Length) is comprised of the backing store capacity extended by the cache capacity." By augmenting the HMAT and SRAT parsing code, this new information can be stored by the HMAT handling code. Current CXL region enumeration code is not enlightened with the side cache configuration and therefore only presents the region size as the size of the CXL region. Add support to allow CXL region enumeration code to query the HMAT handling code and retrieve the information regarding the side cache and adjust the region size accordingly. This should allow the CXL CLI to display the full region size rather than just the CXL only region size. There are 3 sources where the kernel may be notified that error is detected for memory. 1. CXL DRAM event. This is a CXL event that is generated when an error is detected by the CXL device patrol or demand scrubber. The trace_event is augmented to display the aliased System Phyiscal Address (SPA) in addition to the alerted address. However, reporting of memory failure is TBD until the discussion [2] of failure reporting is settled upstream. 2. UCNA event from DRAM patrol or demand scrubber. This should eventually go through the MCE callback chain. 3. MCE from kernel consume poison. It is possible that all 3 sources may report at the same time and all report at the error. For 2 and 3, a MCE notifier callback is registered by the CXL on a per device basis. The callback will determine if the reported address is in one of the special regions and offline the aliased address if that is the case. [1]: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/ [2]: https://lore.kernel.org/linux-cxl/20240808151328.707869-2-ruansy.fnst@fujitsu.com/ --- Dave Jiang (6): ACPICA: actbl1.h: Add extended linear address mode to MSCIS acpi: numa: Add support to enumerate and store extended linear address mode acpi/hmat / cxl: Add extended linear cache support for CXL acpi/hmat: Add helper functions to provide extended linear cache translation cxl: Add extended linear cache address alias emission for cxl events cxl: Add mce notifier to emit aliased address for extended linear cache Documentation/ABI/stable/sysfs-devices-node | 7 ++ arch/x86/include/asm/mce.h | 1 + arch/x86/mm/pat/set_memory.c | 1 + drivers/acpi/numa/hmat.c | 183 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/base/node.c | 2 + drivers/cxl/core/Makefile | 1 + drivers/cxl/core/acpi.c | 21 ++++++ drivers/cxl/core/core.h | 10 +++ drivers/cxl/core/mbox.c | 87 ++++++++++++++++++++++- drivers/cxl/core/region.c | 78 +++++++++++++++++++-- drivers/cxl/core/trace.h | 24 ++++--- drivers/cxl/cxl.h | 8 +++ drivers/cxl/cxlmem.h | 2 + include/acpi/actbl1.h | 5 +- include/linux/acpi.h | 22 ++++++ include/linux/node.h | 7 ++ tools/testing/cxl/Kbuild | 1 + 17 files changed, 443 insertions(+), 17 deletions(-)