| Message ID | 20241017205444.102979-2-gustavo.sousa@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include tx_misc | expand |
Hi, > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of > Patchwork > Sent: Friday, 18 October 2024 2.01 > To: Sousa, Gustavo <gustavo.sousa@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ Fi.CI.BAT: failure for drm/i915/xe2lpd: Update C20 HDMI TMDS > algorithm to include tx_misc > > Patch Details > Series: drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include > tx_misc > URL: https://patchwork.freedesktop.org/series/140136/ > State: failure > Details: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_140136v1/index.html > > CI Bug Log - changes from CI_DRM_15552 -> Patchwork_140136v1 > > > Summary > > > FAILURE > > Serious unknown changes coming with Patchwork_140136v1 absolutely need > to be verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_140136v1, please notify your bug team (I915-ci- > infra@lists.freedesktop.org) to allow them to document this new failure > mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_140136v1/index.html > > > Participating hosts (43 -> 42) > > > Missing (1): fi-snb-2520m > > > Possible new issues > > > Here are the unknown changes that may have been introduced in Patchwork_140136v1: > > > IGT changes > > > Possible regressions > > > * igt@i915_selftest@live@active: > > * fi-glk-j4005: PASS <https://intel-gfx-ci.01.org/tree/drm- > tip/CI_DRM_15552/fi-glk-j4005/igt@i915_selftest@live@active.html> -> > DMESG-FAIL <https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_140136v1/fi-glk-j4005/igt@i915_selftest@live@active.html> Seem known issue but got closed 1,5 months ago: https://gfx-ci.igk.intel.com/cibuglog-ng/issue/14086?query_key=d38d3a2b666aff93008569afe127695ab2dd9418 I guess we need to re-open that? > > > Known issues > > > Here are the changes found in Patchwork_140136v1 that come from known > issues: > > > IGT changes > > > Issues hit > > > * igt@i915_selftest@live: > > * bat-arls-1: PASS <https://intel-gfx-ci.01.org/tree/drm- > tip/CI_DRM_15552/bat-arls-1/igt@i915_selftest@live.html> -> DMESG-FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140136v1/bat-arls- > 1/igt@i915_selftest@live.html> (i915#10262 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10262> / > i915#10341 <https://gitlab.freedesktop.org/drm/i915/kernel/- > /issues/10341> / i915#12133 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133> ) > * fi-glk-j4005: PASS <https://intel-gfx-ci.01.org/tree/drm- > tip/CI_DRM_15552/fi-glk-j4005/igt@i915_selftest@live.html> -> DMESG- > FAIL <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140136v1/fi-glk- > j4005/igt@i915_selftest@live.html> (i915#12133 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133> ) > > * igt@i915_selftest@live@gem_migrate: > > * bat-arls-1: PASS <https://intel-gfx-ci.01.org/tree/drm- > tip/CI_DRM_15552/bat-arls-1/igt@i915_selftest@live@gem_migrate.html> - > > DMESG-WARN <https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_140136v1/bat-arls- > 1/igt@i915_selftest@live@gem_migrate.html> (i915#10341 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341> ) > > * igt@i915_selftest@live@guc_multi_lrc: > > * bat-arls-1: PASS <https://intel-gfx-ci.01.org/tree/drm- > tip/CI_DRM_15552/bat-arls-1/igt@i915_selftest@live@guc_multi_lrc.html> - > > DMESG-FAIL <https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_140136v1/bat-arls- > 1/igt@i915_selftest@live@guc_multi_lrc.html> (i915#10262 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10262> ) +10 > other tests dmesg-fail > > > Possible fixes > > > * igt@i915_module_load@load: > > * bat-adlp-6: DMESG-WARN <https://intel-gfx- > ci.01.org/tree/drm-tip/CI_DRM_15552/bat-adlp- > 6/igt@i915_module_load@load.html> (i915#12253 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12253> ) -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140136v1/bat-adlp- > 6/igt@i915_module_load@load.html> > > * igt@i915_selftest@live: > > * bat-arlh-2: DMESG-FAIL <https://intel-gfx- > ci.01.org/tree/drm-tip/CI_DRM_15552/bat-arlh- > 2/igt@i915_selftest@live.html> (i915#10341 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341> ) -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140136v1/bat-arlh- > 2/igt@i915_selftest@live.html> > > * igt@i915_selftest@live@workarounds: > > * bat-arlh-2: DMESG-FAIL <https://intel-gfx- > ci.01.org/tree/drm-tip/CI_DRM_15552/bat-arlh- > 2/igt@i915_selftest@live@workarounds.html> (i915#9500 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500> ) -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140136v1/bat-arlh- > 2/igt@i915_selftest@live@workarounds.html> > * bat-mtlp-6: ABORT <https://intel-gfx-ci.01.org/tree/drm- > tip/CI_DRM_15552/bat-mtlp-6/igt@i915_selftest@live@workarounds.html> > (i915#12216 <https://gitlab.freedesktop.org/drm/i915/kernel/- > /issues/12216> ) -> PASS <https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_140136v1/bat-mtlp- > 6/igt@i915_selftest@live@workarounds.html> +1 other test pass > > * igt@kms_chamelium_edid@hdmi-edid-read: > > * bat-dg2-13: DMESG-WARN <https://intel-gfx- > ci.01.org/tree/drm-tip/CI_DRM_15552/bat-dg2- > 13/igt@kms_chamelium_edid@hdmi-edid-read.html> -> PASS <https://intel- > gfx-ci.01.org/tree/drm-tip/Patchwork_140136v1/bat-dg2- > 13/igt@kms_chamelium_edid@hdmi-edid-read.html> > > > Build changes > > > * Linux: CI_DRM_15552 -> Patchwork_140136v1 > > CI-20190529: 20190529 > CI_DRM_15552: 4a1a4fc678a06046ca0443a2d0d61f2174c56b1d @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_8078: 175bddf20141ccad40130719ca46bde5140f4872 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_140136v1: 4a1a4fc678a06046ca0443a2d0d61f2174c56b1d @ > git://anongit.freedesktop.org/gfx-ci/linux
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index f73d576fd99e..22184b2d5a11 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2142,8 +2142,12 @@ static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915, i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); } -static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state) +static int intel_c20_compute_hdmi_tmds_pll(struct intel_encoder *encoder, + u64 pixel_clock, + struct intel_c20pll_state *pll_state) { + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + u64 datarate; u64 mpll_tx_clk_div; u64 vco_freq_shift; @@ -2154,6 +2158,7 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_ u64 mpll_fracn_rem; u8 mpllb_ana_freq_vco; u8 mpll_div_multiplier; + u16 tx_misc; if (pixel_clock < 25175 || pixel_clock > 600000) return -EINVAL; @@ -2171,6 +2176,11 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_ mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), datarate), 255); + if (DISPLAY_VER(i915) >= 20) + tx_misc = 0x5; + else + tx_misc = 0x0; + if (vco_freq <= DATARATE_3000000000) mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3; else if (vco_freq <= DATARATE_3500000000) @@ -2182,7 +2192,7 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_ pll_state->clock = pixel_clock; pll_state->tx[0] = 0xbe88; - pll_state->tx[1] = 0x9800; + pll_state->tx[1] = 0x9800 | C20_PHY_TX_MISC(tx_misc); pll_state->tx[2] = 0x0000; pll_state->cmn[0] = 0x0500; pll_state->cmn[1] = 0x0005; @@ -2266,7 +2276,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, /* try computed C20 HDMI tables before using consolidated tables */ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { - if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock, + if (intel_c20_compute_hdmi_tmds_pll(encoder, + crtc_state->port_clock, &crtc_state->dpll_hw_state.cx0pll.c20) == 0) return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index ab3ae110b68f..c1949aa1b909 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -280,6 +280,8 @@ #define PHY_C20_B_TX_CNTX_CFG(i915, idx) \ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx)) #define C20_PHY_TX_RATE REG_GENMASK(2, 0) +#define C20_PHY_TX_MISC_MASK REG_GENMASK(7, 0) +#define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val)) #define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx))
There has been an update to the Bspec in which we need to set tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for Xe2_LPD and newer. That field is mapped to the bits 7:0 of SRAM_GENERIC_<A/B>_TX_CNTX_CFG_1, which in turn translates to tx[1] of our state struct. Update the algorithm to reflect this change. Bspec: 74489 Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++++++++++++++--- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 ++ 2 files changed, 16 insertions(+), 3 deletions(-)