| Message ID | 20241018-qcs8300-mm-patches-v1-4-859095e0776c@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for GPUCC, CAMCC and VIDEOCC on Qualcomm QCS8300 platform | expand |
On Fri, Oct 18, 2024 at 04:42:32PM +0530, Imran Shaik wrote: > Add support to the QCS8300 Camera clock controller by extending > the SA8775P Camera clock controller, which is mostly identical > but QCS8300 has few additional clocks and few other differences. > > Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> > --- > drivers/clk/qcom/camcc-sa8775p.c | 99 ++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 95 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa8775p.c > index c04801a5af35..0ef3c6015c34 100644 > --- a/drivers/clk/qcom/camcc-sa8775p.c > +++ b/drivers/clk/qcom/camcc-sa8775p.c > @@ -1682,6 +1682,24 @@ static struct clk_branch cam_cc_sm_obs_clk = { > }, > }; > > +static struct clk_branch cam_cc_titan_top_accu_shift_clk = { > + .halt_reg = 0x131f0, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x131f0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "cam_cc_titan_top_accu_shift_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &cam_cc_xo_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct gdsc cam_cc_titan_top_gdsc = { > .gdscr = 0x131bc, > .en_rest_wait_val = 0x2, > @@ -1776,6 +1794,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = { > [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, > [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, > [CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr, > + [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL, > [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, > [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, > }; > @@ -1812,6 +1831,7 @@ static struct qcom_cc_desc cam_cc_sa8775p_desc = { > }; > > static const struct of_device_id cam_cc_sa8775p_match_table[] = { > + { .compatible = "qcom,qcs8300-camcc" }, > { .compatible = "qcom,sa8775p-camcc" }, > { } > }; > @@ -1842,10 +1862,81 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev) > clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); > clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); > > - /* Keep some clocks always enabled */ > - qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ > - qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ > - qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ > + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-camcc")) { > + cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154; > + cam_cc_camnoc_axi_clk.halt_reg = 0x1316c; > + cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c; > + cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174; > + cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174; > + > + cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054; > + cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078; > + cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098; > + cam_cc_csid_clk_src.cmd_rcgr = 0x13134; > + > + cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000; > + cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c; > + cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038; > + > + cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104; > + cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c; > + cam_cc_xo_clk_src.cmd_rcgr = 0x131b8; > + cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4; > + > + cam_cc_core_ahb_clk.halt_reg = 0x131b4; > + cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4; > + > + cam_cc_cpas_ahb_clk.halt_reg = 0x130f4; > + cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4; > + cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc; > + cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc; > + > + cam_cc_csi0phytimer_clk.halt_reg = 0x1506c; > + cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c; > + cam_cc_csi1phytimer_clk.halt_reg = 0x15090; > + cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090; > + cam_cc_csi2phytimer_clk.halt_reg = 0x150b0; > + cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0; > + cam_cc_csid_clk.halt_reg = 0x1314c; > + cam_cc_csid_clk.clkr.enable_reg = 0x1314c; > + cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074; > + cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074; > + cam_cc_csiphy0_clk.halt_reg = 0x15070; > + cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070; > + cam_cc_csiphy1_clk.halt_reg = 0x15094; > + cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094; > + cam_cc_csiphy2_clk.halt_reg = 0x150b4; > + cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4; > + > + cam_cc_mclk0_clk.halt_reg = 0x15018; > + cam_cc_mclk0_clk.clkr.enable_reg = 0x15018; > + cam_cc_mclk1_clk.halt_reg = 0x15034; > + cam_cc_mclk1_clk.clkr.enable_reg = 0x15034; > + cam_cc_mclk2_clk.halt_reg = 0x15050; > + cam_cc_mclk2_clk.clkr.enable_reg = 0x15050; > + > + cam_cc_titan_top_gdsc.gdscr = 0x131a0; Ugh. I see the point, but I can't say I like it. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL; > + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL; > + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL; > + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL; > + cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL; > + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL; > + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL; > + cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = > + &cam_cc_titan_top_accu_shift_clk.clkr; > + > + /* Keep some clocks always enabled */ > + qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */ > + qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */ > + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */ > + } else { > + /* Keep some clocks always enabled */ > + qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ > + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ > + qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ > + } > > ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap); > > > -- > 2.25.1 >
diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa8775p.c index c04801a5af35..0ef3c6015c34 100644 --- a/drivers/clk/qcom/camcc-sa8775p.c +++ b/drivers/clk/qcom/camcc-sa8775p.c @@ -1682,6 +1682,24 @@ static struct clk_branch cam_cc_sm_obs_clk = { }, }; +static struct clk_branch cam_cc_titan_top_accu_shift_clk = { + .halt_reg = 0x131f0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x131f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_titan_top_accu_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc cam_cc_titan_top_gdsc = { .gdscr = 0x131bc, .en_rest_wait_val = 0x2, @@ -1776,6 +1794,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = { [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, [CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr, + [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL, [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, }; @@ -1812,6 +1831,7 @@ static struct qcom_cc_desc cam_cc_sa8775p_desc = { }; static const struct of_device_id cam_cc_sa8775p_match_table[] = { + { .compatible = "qcom,qcs8300-camcc" }, { .compatible = "qcom,sa8775p-camcc" }, { } }; @@ -1842,10 +1862,81 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - /* Keep some clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-camcc")) { + cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154; + cam_cc_camnoc_axi_clk.halt_reg = 0x1316c; + cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c; + cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174; + cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174; + + cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054; + cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078; + cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098; + cam_cc_csid_clk_src.cmd_rcgr = 0x13134; + + cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000; + cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c; + cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038; + + cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104; + cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c; + cam_cc_xo_clk_src.cmd_rcgr = 0x131b8; + cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4; + + cam_cc_core_ahb_clk.halt_reg = 0x131b4; + cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4; + + cam_cc_cpas_ahb_clk.halt_reg = 0x130f4; + cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4; + cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc; + cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc; + + cam_cc_csi0phytimer_clk.halt_reg = 0x1506c; + cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c; + cam_cc_csi1phytimer_clk.halt_reg = 0x15090; + cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090; + cam_cc_csi2phytimer_clk.halt_reg = 0x150b0; + cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0; + cam_cc_csid_clk.halt_reg = 0x1314c; + cam_cc_csid_clk.clkr.enable_reg = 0x1314c; + cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074; + cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074; + cam_cc_csiphy0_clk.halt_reg = 0x15070; + cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070; + cam_cc_csiphy1_clk.halt_reg = 0x15094; + cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094; + cam_cc_csiphy2_clk.halt_reg = 0x150b4; + cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4; + + cam_cc_mclk0_clk.halt_reg = 0x15018; + cam_cc_mclk0_clk.clkr.enable_reg = 0x15018; + cam_cc_mclk1_clk.halt_reg = 0x15034; + cam_cc_mclk1_clk.clkr.enable_reg = 0x15034; + cam_cc_mclk2_clk.halt_reg = 0x15050; + cam_cc_mclk2_clk.clkr.enable_reg = 0x15050; + + cam_cc_titan_top_gdsc.gdscr = 0x131a0; + + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL; + cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = + &cam_cc_titan_top_accu_shift_clk.clkr; + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */ + } else { + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + } ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);
Add support to the QCS8300 Camera clock controller by extending the SA8775P Camera clock controller, which is mostly identical but QCS8300 has few additional clocks and few other differences. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> --- drivers/clk/qcom/camcc-sa8775p.c | 99 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 4 deletions(-)