| Message ID | 20241018105505.28005-2-francesco@dolcini.it (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | USB: xhci: add support for PWRON polarity invert (TI TUSB73x0) | expand |
On Fri, Oct 18, 2024 at 12:55:04PM +0200, Francesco Dolcini wrote: > From: Parth Pancholi <parth.pancholi@toradex.com> > > Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI > host controller. The controller supports software configuration > through PCIe registers, such as controlling the PWRONx polarity > via the USB control register (E0h). > > Similar generic PCIe-based bindings can be found as qcom,ath11k-pci.yaml > as an example. > > Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> > --- > v3: use lowercase hex in compatible > v2: rename property to ti,tusb7320-pwron-active-high and change type to flag > --- > .../bindings/usb/ti,tusb73x0-pci.yaml | 60 +++++++++++++++++++ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > > diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > new file mode 100644 > index 000000000000..7083e24d279c > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) > + > +maintainers: > + - Francesco Dolcini <francesco.dolcini@toradex.com> > + > +description: > + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. > + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports up > + to four downstream ports. XHCI controller, should be referencing usb-xhci.yaml. > + > +properties: > + compatible: > + const: pci104c,8241 2 parts mentioned above, but only 1 PCI ID? > + > + reg: > + maxItems: 1 > + > + ti,tusb7320-pwron-active-high: Drop 'tusb7320-' > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Configure the polarity of the PWRONx# signals. When this is present, the PWRONx# > + pins are active high and their internal pull-down resistors are disabled. > + When this is absent, the PWRONx# pins are active low (default) and their internal > + pull-down resistors are enabled. > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + pcie { > + #address-cells = <3>; > + #size-cells = <2>; > + > + pcie@0 { > + device_type = "pci"; You can move this up a level and get rid of this middle node. > + reg = <0x0 0x0 0x0 0x0 0x0>; > + bus-range = <0x01 0xff>; Not needed for examples. > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; > + > + usb@0 { > + compatible = "pci104c,8241"; > + reg = <0x10000 0x0 0x0 0x0 0x0>; In FDT, we generally don't know the bus number because the OS assigns them. So it should always be 0 in 'reg'. Rob
Hello Rob, thanks for the review. On Fri, Oct 18, 2024 at 09:07:43AM -0500, Rob Herring wrote: > On Fri, Oct 18, 2024 at 12:55:04PM +0200, Francesco Dolcini wrote: > > From: Parth Pancholi <parth.pancholi@toradex.com> > > > > Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI > > host controller. The controller supports software configuration > > through PCIe registers, such as controlling the PWRONx polarity > > via the USB control register (E0h). > > > > Similar generic PCIe-based bindings can be found as qcom,ath11k-pci.yaml > > as an example. > > > > Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf > > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > > Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> > > --- > > v3: use lowercase hex in compatible > > v2: rename property to ti,tusb7320-pwron-active-high and change type to flag > > --- > > .../bindings/usb/ti,tusb73x0-pci.yaml | 60 +++++++++++++++++++ > > 1 file changed, 60 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > > > > diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > > new file mode 100644 > > index 000000000000..7083e24d279c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml > > @@ -0,0 +1,60 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) > > + > > +maintainers: > > + - Francesco Dolcini <francesco.dolcini@toradex.com> > > + > > +description: > > + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. > > + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports up > > + to four downstream ports. > > XHCI controller, should be referencing usb-xhci.yaml. > > > + > > +properties: > > + compatible: > > + const: pci104c,8241 > > 2 parts mentioned above, but only 1 PCI ID? Exactly. Let me know if there is something we should do in this regard (something in the commit message? or in the description?). From the datasheet: This 16-bit read only register contains the value 8241h, which is the device ID assigned by TI to the TUSB73X0 And one more confirmation, in the Linux code you have quirks for this device that just check for a single device id: drivers/usb/host/xhci-pci.c:459 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; Francesco
diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml new file mode 100644 index 000000000000..7083e24d279c --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) + +maintainers: + - Francesco Dolcini <francesco.dolcini@toradex.com> + +description: + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports up + to four downstream ports. + +properties: + compatible: + const: pci104c,8241 + + reg: + maxItems: 1 + + ti,tusb7320-pwron-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the polarity of the PWRONx# signals. When this is present, the PWRONx# + pins are active high and their internal pull-down resistors are disabled. + When this is absent, the PWRONx# pins are active low (default) and their internal + pull-down resistors are enabled. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pcie { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + usb@0 { + compatible = "pci104c,8241"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + ti,tusb7320-pwron-active-high; + }; + }; + };