| Message ID | 20241021123414.3993899-2-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for 3 VDSC engines 12 slices | expand |
> -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Monday, October 21, 2024 6:04 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj > <suraj.kandpal@intel.com> > Subject: [PATCH 01/16] drm/i915/dp: Update Comment for Valid DSC Slices > per Line > > For some platforms, the maximum slices per DSC engine is 4, while for > others it is 2. Update the comment to reflect this and clarify that the > 'valid_dsc_slicecount' list represents the valid number of slices per pipe. > > Currently, we are working with 1, and 2 slices per DSC engine, which works > for all platforms. With this the number of slices per pipe can be 1,2 or 4 > with different slice & DSC engine configuration. > > Add a #TODO for adding support for 4 slices per DSC engine where > supported. LGTM, Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 7e04913bc2ff..286b272aa98c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -108,8 +108,14 @@ > /* Constants for DP DSC configurations */ static const u8 valid_dsc_bpp[] = > {6, 8, 10, 12, 15}; > > -/* With Single pipe configuration, HW is capable of supporting maximum > - * of 4 slices per line. > +/* > + * With Single pipe configuration, HW is capable of supporting maximum > of: > + * 2 slices per line for ICL, BMG > + * 4 slices per line for other platforms. > + * For now consider a max of 2 slices per line, which works for all > platforms. > + * With this we can have max of 4 DSC Slices per pipe. > + * > + * #TODO Split this better to use 4 slices/dsc engine where supported. > */ > static const u8 valid_dsc_slicecount[] = {1, 2, 4}; > > -- > 2.45.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7e04913bc2ff..286b272aa98c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -108,8 +108,14 @@ /* Constants for DP DSC configurations */ static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; -/* With Single pipe configuration, HW is capable of supporting maximum - * of 4 slices per line. +/* + * With Single pipe configuration, HW is capable of supporting maximum of: + * 2 slices per line for ICL, BMG + * 4 slices per line for other platforms. + * For now consider a max of 2 slices per line, which works for all platforms. + * With this we can have max of 4 DSC Slices per pipe. + * + * #TODO Split this better to use 4 slices/dsc engine where supported. */ static const u8 valid_dsc_slicecount[] = {1, 2, 4};
For some platforms, the maximum slices per DSC engine is 4, while for others it is 2. Update the comment to reflect this and clarify that the 'valid_dsc_slicecount' list represents the valid number of slices per pipe. Currently, we are working with 1, and 2 slices per DSC engine, which works for all platforms. With this the number of slices per pipe can be 1,2 or 4 with different slice & DSC engine configuration. Add a #TODO for adding support for 4 slices per DSC engine where supported. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)