| Message ID | 20241021081311.543625-1-fshao@chromium.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: mediatek: mt8188: Fix USB3 PHY port default status | expand |
On Mon, 21 Oct 2024 16:10:47 +0800, Fei Shao wrote: > The T-PHY controller at 0x11e40000 controls two underlying USB2 and USB3 > PHY ports. The USB3 port works normally just like the others, so there's > no point in disabling it separately. Otherwise, board DTs would have to > enable both the T-PHY controller and one of its sub-nodes in particular, > which is slightly redundant and confusing. > > Remove the status line in the u3port1 node, so it's ready to be used > once the T-PHY controller is enabled. > > [...] Applied to v6.12-next/dts64, thanks! [1/1] arm64: dts: mediatek: mt8188: Fix USB3 PHY port default status commit: 6bb64877a41561bc78e0f4e9e04d524a0155d6aa Cheers, Angelo
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 2710e18ce696..3d11a989f39f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1961,7 +1961,6 @@ u3port1: usb-phy@700 { <&clk26m>; clock-names = "ref", "da_ref"; #phy-cells = <1>; - status = "disabled"; }; };
The T-PHY controller at 0x11e40000 controls two underlying USB2 and USB3 PHY ports. The USB3 port works normally just like the others, so there's no point in disabling it separately. Otherwise, board DTs would have to enable both the T-PHY controller and one of its sub-nodes in particular, which is slightly redundant and confusing. Remove the status line in the u3port1 node, so it's ready to be used once the T-PHY controller is enabled. Fixes: 9461e0caac9e ("arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile") Signed-off-by: Fei Shao <fshao@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 1 - 1 file changed, 1 deletion(-)