| Message ID | 20241008164935.335043-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 9ddc07404cbab0aee36b076b627ad9ecb7bb2290 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [v2] arm64: dts: renesas: r9a09g057: Add OPP table | expand |
Hi Prabhakar, > -----Original Message----- > From: Prabhakar <prabhakar.csengg@gmail.com> > Sent: Tuesday, October 8, 2024 5:50 PM > Subject: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add OPP table for RZ/V2H(P) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1->v2 > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > --- > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > index 1ad5a1b6917f..4bbe75b81f54 100644 > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > clock-frequency = <0>; > }; > > + /* > + * The default cluster table is based on the assumption that the PLLCA55 clock > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > + * clocked to 1.8GHz as well). The table below should be overridden in the board > + * DTS based on the PLLCA55 clock frequency. > + */ > + cluster0_opp: opp-table-0 { > + compatible = "operating-points-v2"; > + > + opp-1700000000 { > + opp-hz = /bits/ 64 <1700000000>; > + opp-microvolt = <900000>; Not sure CA-55 can change voltage from 800mV to 900mV?? Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. The manual says OD voltage is 0.9V and ND voltage is 0.8V. Is 1.7GHZ is ND or OD? Cheers, Biju > + clock-latency-ns = <300000>; > + }; > + opp-850000000 { > + opp-hz = /bits/ 64 <850000000>; > + opp-microvolt = <800000>; > + clock-latency-ns = <300000>; > + }; > + opp-425000000 { > + opp-hz = /bits/ 64 <425000000>; > + opp-microvolt = <800000>; > + clock-latency-ns = <300000>; > + }; > + opp-212500000 { > + opp-hz = /bits/ 64 <212500000>; > + opp-microvolt = <800000>; > + clock-latency-ns = <300000>; > + opp-suspend; > + }; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -30,6 +63,8 @@ cpu0: cpu@0 { > device_type = "cpu"; > next-level-cache = <&L3_CA55>; > enable-method = "psci"; > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu1: cpu@100 { > @@ -38,6 +73,8 @@ cpu1: cpu@100 { > device_type = "cpu"; > next-level-cache = <&L3_CA55>; > enable-method = "psci"; > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu2: cpu@200 { > @@ -46,6 +83,8 @@ cpu2: cpu@200 { > device_type = "cpu"; > next-level-cache = <&L3_CA55>; > enable-method = "psci"; > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu3: cpu@300 { > @@ -54,6 +93,8 @@ cpu3: cpu@300 { > device_type = "cpu"; > next-level-cache = <&L3_CA55>; > enable-method = "psci"; > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; > + operating-points-v2 = <&cluster0_opp>; > }; > > L3_CA55: cache-controller-0 { > -- > 2.43.0
> -----Original Message----- > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: Tuesday, October 8, 2024 6:19 PM > Subject: RE: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > Hi Prabhakar, > > > -----Original Message----- > > From: Prabhakar <prabhakar.csengg@gmail.com> > > Sent: Tuesday, October 8, 2024 5:50 PM > > Subject: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add OPP table for RZ/V2H(P) SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > > --- > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++ > > 1 file changed, 41 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > clock-frequency = <0>; > > }; > > > > + /* > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > + * DTS based on the PLLCA55 clock frequency. > > + */ > > + cluster0_opp: opp-table-0 { > > + compatible = "operating-points-v2"; > > + > > + opp-1700000000 { > > + opp-hz = /bits/ 64 <1700000000>; > > + opp-microvolt = <900000>; > > Not sure CA-55 can change voltage from 800mV to 900mV?? > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > Is 1.7GHZ is ND or OD? {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V and for 1.1 GHz it is 0.8V. Maybe when you do /2, /4, /8 using dividers, the voltage may be still the same?? Cheers, Biju > > > > + clock-latency-ns = <300000>; > > + }; > > + opp-850000000 { > > + opp-hz = /bits/ 64 <850000000>; > > + opp-microvolt = <800000>; > > + clock-latency-ns = <300000>; > > + }; > > + opp-425000000 { > > + opp-hz = /bits/ 64 <425000000>; > > + opp-microvolt = <800000>; > > + clock-latency-ns = <300000>; > > + }; > > + opp-212500000 { > > + opp-hz = /bits/ 64 <212500000>; > > + opp-microvolt = <800000>; > > + clock-latency-ns = <300000>; > > + opp-suspend; > > + }; > > + }; > > + > > cpus { > > #address-cells = <1>; > > #size-cells = <0>; > > @@ -30,6 +63,8 @@ cpu0: cpu@0 { > > device_type = "cpu"; > > next-level-cache = <&L3_CA55>; > > enable-method = "psci"; > > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; > > + operating-points-v2 = <&cluster0_opp>; > > }; > > > > cpu1: cpu@100 { > > @@ -38,6 +73,8 @@ cpu1: cpu@100 { > > device_type = "cpu"; > > next-level-cache = <&L3_CA55>; > > enable-method = "psci"; > > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; > > + operating-points-v2 = <&cluster0_opp>; > > }; > > > > cpu2: cpu@200 { > > @@ -46,6 +83,8 @@ cpu2: cpu@200 { > > device_type = "cpu"; > > next-level-cache = <&L3_CA55>; > > enable-method = "psci"; > > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; > > + operating-points-v2 = <&cluster0_opp>; > > }; > > > > cpu3: cpu@300 { > > @@ -54,6 +93,8 @@ cpu3: cpu@300 { > > device_type = "cpu"; > > next-level-cache = <&L3_CA55>; > > enable-method = "psci"; > > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; > > + operating-points-v2 = <&cluster0_opp>; > > }; > > > > L3_CA55: cache-controller-0 { > > -- > > 2.43.0 >
Hi Biju, On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > -----Original Message----- > > From: Biju Das <biju.das.jz@bp.renesas.com> > > Sent: Tuesday, October 8, 2024 6:19 PM > > Subject: RE: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > > > Hi Prabhakar, > > > > > -----Original Message----- > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > Sent: Tuesday, October 8, 2024 5:50 PM > > > Subject: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > --- > > > v1->v2 > > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > > > --- > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++ > > > 1 file changed, 41 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > clock-frequency = <0>; > > > }; > > > > > > + /* > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > + * DTS based on the PLLCA55 clock frequency. > > > + */ > > > + cluster0_opp: opp-table-0 { > > > + compatible = "operating-points-v2"; > > > + > > > + opp-1700000000 { > > > + opp-hz = /bits/ 64 <1700000000>; > > > + opp-microvolt = <900000>; > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > Is 1.7GHZ is ND or OD? > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V > and for 1.1 GHz it is 0.8V. > > Maybe when you do /2, /4, /8 using dividers, the voltage may be still > the same?? > I think you are right when BOOTPLLCA[1:0] pins are set to 1.7GHz the VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt affect the voltage levels at the PMIC output. Geert, please let me know if my understanding is incorrect. Cheers, Prabhakar
Hi Prabhakar, On Tue, Oct 8, 2024 at 10:10 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > --- > > > > v1->v2 > > > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > > > > --- > > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++ > > > > 1 file changed, 41 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > > clock-frequency = <0>; > > > > }; > > > > > > > > + /* > > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > > + * DTS based on the PLLCA55 clock frequency. > > > > + */ > > > > + cluster0_opp: opp-table-0 { > > > > + compatible = "operating-points-v2"; > > > > + > > > > + opp-1700000000 { > > > > + opp-hz = /bits/ 64 <1700000000>; > > > > + opp-microvolt = <900000>; > > > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. > > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > > > Is 1.7GHZ is ND or OD? > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V > > and for 1.1 GHz it is 0.8V. > > > > Maybe when you do /2, /4, /8 using dividers, the voltage may be still > > the same?? > > > I think you are right when BOOTPLLCA[1:0] pins are set to 1.7GHz the > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt affect the > voltage levels at the PMIC output. > > Geert, please let me know if my understanding is incorrect. The actual VDD09_CA55 voltage is controlled by the external PMIC (RAA215300). It is the responsibility of the system designer to make sure VDD09_CA55 is at 0.9V when BOOTPLLCA[1:0] is strapped for OD, as CPU core clock rates higher than 1.1 GHz need a higher core voltage. I don't think it hurts to supply the higher core voltage while running the CPU core at low core frequencies, except for extra power consumption. To control VDD09_CA55 dynamically, the CPU cores should have cpu-supply properties pointing to the regulator controlling it (raa215300). I haven't checked how Linux behaves when no cpu-supply property is present, or when it points to a fixed regulator. I am also wondering if other opps (1.1/1.5/1.6/1.8 GHz) should be added, too? And probably any opp above 1.1GHz opp should be tagged with "turbo-mode"? Gr{oetje,eeting}s, Geert
Hi Geert, > -----Original Message----- > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: Wednesday, October 9, 2024 10:28 AM > Subject: Re: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > Hi Prabhakar, > > On Tue, Oct 8, 2024 at 10:10 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > --- > > > > > v1->v2 > > > > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > > > > > --- > > > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 > > > > > ++++++++++++++++++++++ > > > > > 1 file changed, 41 insertions(+) > > > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > > > clock-frequency = <0>; > > > > > }; > > > > > > > > > > + /* > > > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > > > + * DTS based on the PLLCA55 clock frequency. > > > > > + */ > > > > > + cluster0_opp: opp-table-0 { > > > > > + compatible = "operating-points-v2"; > > > > > + > > > > > + opp-1700000000 { > > > > > + opp-hz = /bits/ 64 <1700000000>; > > > > > + opp-microvolt = <900000>; > > > > > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > > > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. > > > > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > > > > > Is 1.7GHZ is ND or OD? > > > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V and for 1.1 > > > GHz it is 0.8V. > > > > > > Maybe when you do /2, /4, /8 using dividers, the voltage may be > > > still the same?? > > > > > I think you are right when BOOTPLLCA[1:0] pins are set to 1.7GHz the > > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt affect the > > voltage levels at the PMIC output. > > > > Geert, please let me know if my understanding is incorrect. > > The actual VDD09_CA55 voltage is controlled by the external PMIC (RAA215300). It is the > responsibility of the system designer to make sure VDD09_CA55 is at 0.9V when BOOTPLLCA[1:0] is > strapped for OD, as CPU core clock rates higher than 1.1 GHz need a higher core voltage. > I don't think it hurts to supply the higher core voltage while running the CPU core at low core > frequencies, except for extra power consumption. > > To control VDD09_CA55 dynamically, the CPU cores should have cpu-supply properties pointing to the > regulator controlling it (raa215300). This needs a big work(see: 4.5.3.1.3 PD_CA55 area voltage change). CA-55 needs to signal CM-33 so that it switches to AWO mode(Only CM-33 is active) and In AWO mode, CM33 is in charge of changing CA55 voltage and then switches to ALL-ON mode Cheers. Biju
Hi Biju, On Wed, Oct 9, 2024 at 11:41 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > From: Geert Uytterhoeven <geert@linux-m68k.org> > > On Tue, Oct 8, 2024 at 10:10 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > --- > > > > > > v1->v2 > > > > > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > > > > > > --- > > > > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 > > > > > > ++++++++++++++++++++++ > > > > > > 1 file changed, 41 insertions(+) > > > > > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > > > > clock-frequency = <0>; > > > > > > }; > > > > > > > > > > > > + /* > > > > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > > > > + * DTS based on the PLLCA55 clock frequency. > > > > > > + */ > > > > > > + cluster0_opp: opp-table-0 { > > > > > > + compatible = "operating-points-v2"; > > > > > > + > > > > > > + opp-1700000000 { > > > > > > + opp-hz = /bits/ 64 <1700000000>; > > > > > > + opp-microvolt = <900000>; > > > > > > > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > > > > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. > > > > > > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > > > > > > > Is 1.7GHZ is ND or OD? > > > > > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V and for 1.1 > > > > GHz it is 0.8V. > > > > > > > > Maybe when you do /2, /4, /8 using dividers, the voltage may be > > > > still the same?? > > > > > > > I think you are right when BOOTPLLCA[1:0] pins are set to 1.7GHz the > > > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt affect the > > > voltage levels at the PMIC output. > > > > > > Geert, please let me know if my understanding is incorrect. > > > > The actual VDD09_CA55 voltage is controlled by the external PMIC (RAA215300). It is the > > responsibility of the system designer to make sure VDD09_CA55 is at 0.9V when BOOTPLLCA[1:0] is > > strapped for OD, as CPU core clock rates higher than 1.1 GHz need a higher core voltage. > > I don't think it hurts to supply the higher core voltage while running the CPU core at low core > > frequencies, except for extra power consumption. > > > > To control VDD09_CA55 dynamically, the CPU cores should have cpu-supply properties pointing to the > > regulator controlling it (raa215300). > > This needs a big work(see: 4.5.3.1.3 PD_CA55 area voltage change). > CA-55 needs to signal CM-33 so that it switches to AWO mode(Only CM-33 is active) and > In AWO mode, CM33 is in charge of changing CA55 voltage and then switches to ALL-ON mode > Ugh, this is indeed much more complicated than on other SoCs. So basically you are stuck with the initial voltage settings. Gr{oetje,eeting}s, Geert
Hi Geert, > -----Original Message----- > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: Wednesday, October 9, 2024 11:09 AM > Subject: Re: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > Hi Biju, > > On Wed, Oct 9, 2024 at 11:41 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, Oct 8, 2024 > > > at 10:10 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > > From: Lad Prabhakar > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > --- > > > > > > > v1->v2 > > > > > > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > > > > > > > --- > > > > > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 > > > > > > > ++++++++++++++++++++++ > > > > > > > 1 file changed, 41 insertions(+) > > > > > > > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > > > > > clock-frequency = <0>; > > > > > > > }; > > > > > > > > > > > > > > + /* > > > > > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > > > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > > > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > > > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > > > > > + * DTS based on the PLLCA55 clock frequency. > > > > > > > + */ > > > > > > > + cluster0_opp: opp-table-0 { > > > > > > > + compatible = "operating-points-v2"; > > > > > > > + > > > > > > > + opp-1700000000 { > > > > > > > + opp-hz = /bits/ 64 <1700000000>; > > > > > > > + opp-microvolt = <900000>; > > > > > > > > > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > > > > > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. > > > > > > > > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > > > > > > > > > Is 1.7GHZ is ND or OD? > > > > > > > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V and for > > > > > 1.1 GHz it is 0.8V. > > > > > > > > > > Maybe when you do /2, /4, /8 using dividers, the voltage may be > > > > > still the same?? > > > > > > > > > I think you are right when BOOTPLLCA[1:0] pins are set to 1.7GHz > > > > the > > > > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt affect > > > > the voltage levels at the PMIC output. > > > > > > > > Geert, please let me know if my understanding is incorrect. > > > > > > The actual VDD09_CA55 voltage is controlled by the external PMIC > > > (RAA215300). It is the responsibility of the system designer to > > > make sure VDD09_CA55 is at 0.9V when BOOTPLLCA[1:0] is strapped for OD, as CPU core clock rates > higher than 1.1 GHz need a higher core voltage. > > > I don't think it hurts to supply the higher core voltage while > > > running the CPU core at low core frequencies, except for extra power consumption. > > > > > > To control VDD09_CA55 dynamically, the CPU cores should have > > > cpu-supply properties pointing to the regulator controlling it (raa215300). > > > > This needs a big work(see: 4.5.3.1.3 PD_CA55 area voltage change). > > CA-55 needs to signal CM-33 so that it switches to AWO mode(Only CM-33 > > is active) and In AWO mode, CM33 is in charge of changing CA55 voltage > > and then switches to ALL-ON mode > > > > Ugh, this is indeed much more complicated than on other SoCs. > So basically you are stuck with the initial voltage settings. FYI, I got confirmation that 1.7GHz,0.9V is Normal drive and It is the default for RZ/V2H and upcoming RZ/G3E SoCs. Cheers, Biju
Hi Biju, On Fri, Oct 11, 2024 at 9:43 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > From: Geert Uytterhoeven <geert@linux-m68k.org> > > On Wed, Oct 9, 2024 at 11:41 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, Oct 8, 2024 > > > > at 10:10 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > > > From: Lad Prabhakar > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > --- > > > > > > > > v1->v2 > > > > > > > > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > > > > > > > > --- > > > > > > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 > > > > > > > > ++++++++++++++++++++++ > > > > > > > > 1 file changed, 41 insertions(+) > > > > > > > > > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > > > > > > clock-frequency = <0>; > > > > > > > > }; > > > > > > > > > > > > > > > > + /* > > > > > > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > > > > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > > > > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > > > > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > > > > > > + * DTS based on the PLLCA55 clock frequency. > > > > > > > > + */ > > > > > > > > + cluster0_opp: opp-table-0 { > > > > > > > > + compatible = "operating-points-v2"; > > > > > > > > + > > > > > > > > + opp-1700000000 { > > > > > > > > + opp-hz = /bits/ 64 <1700000000>; > > > > > > > > + opp-microvolt = <900000>; > > > > > > > > > > > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > > > > > > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. > > > > > > > > > > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > > > > > > > > > > > Is 1.7GHZ is ND or OD? > > > > > > > > > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V and for > > > > > > 1.1 GHz it is 0.8V. > > > > > > > > > > > > Maybe when you do /2, /4, /8 using dividers, the voltage may be > > > > > > still the same?? > > > > > > > > > > > I think you are right when BOOTPLLCA[1:0] pins are set to 1.7GHz > > > > > the > > > > > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt affect > > > > > the voltage levels at the PMIC output. > > > > > > > > > > Geert, please let me know if my understanding is incorrect. > > > > > > > > The actual VDD09_CA55 voltage is controlled by the external PMIC > > > > (RAA215300). It is the responsibility of the system designer to > > > > make sure VDD09_CA55 is at 0.9V when BOOTPLLCA[1:0] is strapped for OD, as CPU core clock rates > > higher than 1.1 GHz need a higher core voltage. > > > > I don't think it hurts to supply the higher core voltage while > > > > running the CPU core at low core frequencies, except for extra power consumption. > > > > > > > > To control VDD09_CA55 dynamically, the CPU cores should have > > > > cpu-supply properties pointing to the regulator controlling it (raa215300). > > > > > > This needs a big work(see: 4.5.3.1.3 PD_CA55 area voltage change). > > > CA-55 needs to signal CM-33 so that it switches to AWO mode(Only CM-33 > > > is active) and In AWO mode, CM33 is in charge of changing CA55 voltage > > > and then switches to ALL-ON mode > > > > Ugh, this is indeed much more complicated than on other SoCs. > > So basically you are stuck with the initial voltage settings. > > FYI, I got confirmation that 1.7GHz,0.9V is Normal drive and > It is the default for RZ/V2H and upcoming RZ/G3E SoCs. OK, so no "turbo-mode" property is needed. And hence this patch is good as-is? Thanks! Gr{oetje,eeting}s, Geert
Hi Geert, > -----Original Message----- > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: Friday, October 11, 2024 8:48 AM > Subject: Re: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > Hi Biju, > > On Fri, Oct 11, 2024 at 9:43 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, Oct 9, 2024 > > > at 11:41 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, Oct 8, > > > > > 2024 at 10:10 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > > > > From: Lad Prabhakar > > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > > > > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > --- > > > > > > > > > v1->v2 > > > > > > > > > - Set opp-microvolt to 800000 for frequencies below > > > > > > > > > 1.1GHz > > > > > > > > > --- > > > > > > > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 > > > > > > > > > ++++++++++++++++++++++ > > > > > > > > > 1 file changed, 41 insertions(+) > > > > > > > > > > > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > > > > > > > clock-frequency = <0>; > > > > > > > > > }; > > > > > > > > > > > > > > > > > > + /* > > > > > > > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > > > > > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > > > > > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > > > > > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > > > > > > > + * DTS based on the PLLCA55 clock frequency. > > > > > > > > > + */ > > > > > > > > > + cluster0_opp: opp-table-0 { > > > > > > > > > + compatible = "operating-points-v2"; > > > > > > > > > + > > > > > > > > > + opp-1700000000 { > > > > > > > > > + opp-hz = /bits/ 64 <1700000000>; > > > > > > > > > + opp-microvolt = <900000>; > > > > > > > > > > > > > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > > > > > > > Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 > voltage. > > > > > > > > > > > > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > > > > > > > > > > > > > Is 1.7GHZ is ND or OD? > > > > > > > > > > > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V and > > > > > > > for > > > > > > > 1.1 GHz it is 0.8V. > > > > > > > > > > > > > > Maybe when you do /2, /4, /8 using dividers, the voltage may > > > > > > > be still the same?? > > > > > > > > > > > > > I think you are right when BOOTPLLCA[1:0] pins are set to > > > > > > 1.7GHz the > > > > > > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt > > > > > > affect the voltage levels at the PMIC output. > > > > > > > > > > > > Geert, please let me know if my understanding is incorrect. > > > > > > > > > > The actual VDD09_CA55 voltage is controlled by the external PMIC > > > > > (RAA215300). It is the responsibility of the system designer to > > > > > make sure VDD09_CA55 is at 0.9V when BOOTPLLCA[1:0] is strapped > > > > > for OD, as CPU core clock rates > > > higher than 1.1 GHz need a higher core voltage. > > > > > I don't think it hurts to supply the higher core voltage while > > > > > running the CPU core at low core frequencies, except for extra power consumption. > > > > > > > > > > To control VDD09_CA55 dynamically, the CPU cores should have > > > > > cpu-supply properties pointing to the regulator controlling it (raa215300). > > > > > > > > This needs a big work(see: 4.5.3.1.3 PD_CA55 area voltage change). > > > > CA-55 needs to signal CM-33 so that it switches to AWO mode(Only > > > > CM-33 is active) and In AWO mode, CM33 is in charge of changing > > > > CA55 voltage and then switches to ALL-ON mode > > > > > > Ugh, this is indeed much more complicated than on other SoCs. > > > So basically you are stuck with the initial voltage settings. > > > > FYI, I got confirmation that 1.7GHz,0.9V is Normal drive and It is the > > default for RZ/V2H and upcoming RZ/G3E SoCs. > > OK, so no "turbo-mode" property is needed. "turbo-mode" is 1.8GHz "1.8GHz cannot be supported by CA55 only (CM33 is required) so upstream target is 1.7GHz." So, without CM-33, turbo-mode is not possible?? We are rechecking this and will provide feedback once we get info from HW people. Cheers, Biju
Hi Geert, > -----Original Message----- > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: Friday, October 11, 2024 9:00 AM > Subject: RE: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > Hi Geert, > > > -----Original Message----- > > From: Geert Uytterhoeven <geert@linux-m68k.org> > > Sent: Friday, October 11, 2024 8:48 AM > > Subject: Re: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > > > Hi Biju, > > > > On Fri, Oct 11, 2024 at 9:43 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, Oct 9, > > > > 2024 at 11:41 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, Oct 8, > > > > > > 2024 at 10:10 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > > > > > From: Lad Prabhakar > > > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > > > > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > --- > > > > > > > > > > v1->v2 > > > > > > > > > > - Set opp-microvolt to 800000 for frequencies below > > > > > > > > > > 1.1GHz > > > > > > > > > > --- > > > > > > > > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 > > > > > > > > > > ++++++++++++++++++++++ > > > > > > > > > > 1 file changed, 41 insertions(+) > > > > > > > > > > > > > > > > > > > > diff --git > > > > > > > > > > a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > > > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > > > > > > > > clock-frequency = <0>; > > > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > + /* > > > > > > > > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > > > > > > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > > > > > > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > > > > > > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > > > > > > > > + * DTS based on the PLLCA55 clock frequency. > > > > > > > > > > + */ > > > > > > > > > > + cluster0_opp: opp-table-0 { > > > > > > > > > > + compatible = "operating-points-v2"; > > > > > > > > > > + > > > > > > > > > > + opp-1700000000 { > > > > > > > > > > + opp-hz = /bits/ 64 <1700000000>; > > > > > > > > > > + opp-microvolt = <900000>; > > > > > > > > > > > > > > > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > > > > > > > > Based on Power Domain Control, it needs to be in AWO > > > > > > > > > mode for changing the PD_CA55 > > voltage. > > > > > > > > > > > > > > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > > > > > > > > > > > > > > > Is 1.7GHZ is ND or OD? > > > > > > > > > > > > > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V > > > > > > > > and for > > > > > > > > 1.1 GHz it is 0.8V. > > > > > > > > > > > > > > > > Maybe when you do /2, /4, /8 using dividers, the voltage > > > > > > > > may be still the same?? > > > > > > > > > > > > > > > I think you are right when BOOTPLLCA[1:0] pins are set to > > > > > > > 1.7GHz the > > > > > > > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt > > > > > > > affect the voltage levels at the PMIC output. > > > > > > > > > > > > > > Geert, please let me know if my understanding is incorrect. > > > > > > > > > > > > The actual VDD09_CA55 voltage is controlled by the external > > > > > > PMIC (RAA215300). It is the responsibility of the system > > > > > > designer to make sure VDD09_CA55 is at 0.9V when > > > > > > BOOTPLLCA[1:0] is strapped for OD, as CPU core clock rates > > > > higher than 1.1 GHz need a higher core voltage. > > > > > > I don't think it hurts to supply the higher core voltage while > > > > > > running the CPU core at low core frequencies, except for extra power consumption. > > > > > > > > > > > > To control VDD09_CA55 dynamically, the CPU cores should have > > > > > > cpu-supply properties pointing to the regulator controlling it (raa215300). > > > > > > > > > > This needs a big work(see: 4.5.3.1.3 PD_CA55 area voltage change). > > > > > CA-55 needs to signal CM-33 so that it switches to AWO mode(Only > > > > > CM-33 is active) and In AWO mode, CM33 is in charge of changing > > > > > CA55 voltage and then switches to ALL-ON mode > > > > > > > > Ugh, this is indeed much more complicated than on other SoCs. > > > > So basically you are stuck with the initial voltage settings. > > > > > > FYI, I got confirmation that 1.7GHz,0.9V is Normal drive and It is > > > the default for RZ/V2H and upcoming RZ/G3E SoCs. > > > > OK, so no "turbo-mode" property is needed. > > "turbo-mode" is 1.8GHz > > "1.8GHz cannot be supported by CA55 only (CM33 is required) so upstream target is 1.7GHz." > > So, without CM-33, turbo-mode is not possible?? We are rechecking this and will provide feedback once > we get info from HW people. Got update from HW team. From HW point of view, 1.8GHz, 0.9V is over drive and 1.1GHz, 0.8V is normal drive. but for achieving 1.8GHz, CM33 is required. So no "turbo-mode" property is needed. But viewpoint from Linux, 1.7GHz, 0.9V is over drive and 1.1GHz, 0.8V is normal drive and 1.7GHz should be the upstream target. As you said, looks like the current patch is good enough. Cheers, Biju
Hi Biju, On Wed, Oct 23, 2024 at 3:04 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > From: Geert Uytterhoeven <geert@linux-m68k.org> > > > On Fri, Oct 11, 2024 at 9:43 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, Oct 9, > > > > > 2024 at 11:41 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, Oct 8, > > > > > > > 2024 at 10:10 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > On Tue, Oct 8, 2024 at 6:33 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > > > > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > > > > > > > From: Lad Prabhakar > > > > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > > > > > > > > > > > Add OPP table for RZ/V2H(P) SoC. > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > --- > > > > > > > > > > > v1->v2 > > > > > > > > > > > - Set opp-microvolt to 800000 for frequencies below > > > > > > > > > > > 1.1GHz > > > > > > > > > > > --- > > > > > > > > > > > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 > > > > > > > > > > > ++++++++++++++++++++++ > > > > > > > > > > > 1 file changed, 41 insertions(+) > > > > > > > > > > > > > > > > > > > > > > diff --git > > > > > > > > > > > a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > > > index 1ad5a1b6917f..4bbe75b81f54 100644 > > > > > > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > > > > > > > > > > > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > > > > > > > > > > > clock-frequency = <0>; > > > > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > > > + /* > > > > > > > > > > > + * The default cluster table is based on the assumption that the PLLCA55 clock > > > > > > > > > > > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > > > > > > > > > > > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > > > > > > > > > > > + * clocked to 1.8GHz as well). The table below should be overridden in the board > > > > > > > > > > > + * DTS based on the PLLCA55 clock frequency. > > > > > > > > > > > + */ > > > > > > > > > > > + cluster0_opp: opp-table-0 { > > > > > > > > > > > + compatible = "operating-points-v2"; > > > > > > > > > > > + > > > > > > > > > > > + opp-1700000000 { > > > > > > > > > > > + opp-hz = /bits/ 64 <1700000000>; > > > > > > > > > > > + opp-microvolt = <900000>; > > > > > > > > > > > > > > > > > > > > Not sure CA-55 can change voltage from 800mV to 900mV?? > > > > > > > > > > Based on Power Domain Control, it needs to be in AWO > > > > > > > > > > mode for changing the PD_CA55 > > > voltage. > > > > > > > > > > > > > > > > > > > > The manual says OD voltage is 0.9V and ND voltage is 0.8V. > > > > > > > > > > > > > > > > > > > > Is 1.7GHZ is ND or OD? > > > > > > > > > > > > > > > > > > {1.7,1.6,1.5 GHz} is enabled when VDD09_CA55 is at 0.9 V > > > > > > > > > and for > > > > > > > > > 1.1 GHz it is 0.8V. > > > > > > > > > > > > > > > > > > Maybe when you do /2, /4, /8 using dividers, the voltage > > > > > > > > > may be still the same?? > > > > > > > > > > > > > > > > > I think you are right when BOOTPLLCA[1:0] pins are set to > > > > > > > > 1.7GHz the > > > > > > > > VDD09_CA55 is at 0.9 V, further dividing the clock shouldnt > > > > > > > > affect the voltage levels at the PMIC output. > > > > > > > > > > > > > > > > Geert, please let me know if my understanding is incorrect. > > > > > > > > > > > > > > The actual VDD09_CA55 voltage is controlled by the external > > > > > > > PMIC (RAA215300). It is the responsibility of the system > > > > > > > designer to make sure VDD09_CA55 is at 0.9V when > > > > > > > BOOTPLLCA[1:0] is strapped for OD, as CPU core clock rates > > > > > higher than 1.1 GHz need a higher core voltage. > > > > > > > I don't think it hurts to supply the higher core voltage while > > > > > > > running the CPU core at low core frequencies, except for extra power consumption. > > > > > > > > > > > > > > To control VDD09_CA55 dynamically, the CPU cores should have > > > > > > > cpu-supply properties pointing to the regulator controlling it (raa215300). > > > > > > > > > > > > This needs a big work(see: 4.5.3.1.3 PD_CA55 area voltage change). > > > > > > CA-55 needs to signal CM-33 so that it switches to AWO mode(Only > > > > > > CM-33 is active) and In AWO mode, CM33 is in charge of changing > > > > > > CA55 voltage and then switches to ALL-ON mode > > > > > > > > > > Ugh, this is indeed much more complicated than on other SoCs. > > > > > So basically you are stuck with the initial voltage settings. > > > > > > > > FYI, I got confirmation that 1.7GHz,0.9V is Normal drive and It is > > > > the default for RZ/V2H and upcoming RZ/G3E SoCs. > > > > > > OK, so no "turbo-mode" property is needed. > > > > "turbo-mode" is 1.8GHz > > > > "1.8GHz cannot be supported by CA55 only (CM33 is required) so upstream target is 1.7GHz." > > > > So, without CM-33, turbo-mode is not possible?? We are rechecking this and will provide feedback once > > we get info from HW people. > > Got update from HW team. > > From HW point of view, 1.8GHz, 0.9V is over drive and 1.1GHz, 0.8V is normal drive. > but for achieving 1.8GHz, CM33 is required. So no "turbo-mode" property is needed. > > But viewpoint from Linux, 1.7GHz, 0.9V is over drive and 1.1GHz, 0.8V is normal drive > and 1.7GHz should be the upstream target. Thanks for the follow-up! > As you said, looks like the current patch is good enough. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.13. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 1ad5a1b6917f..4bbe75b81f54 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + /* + * The default cluster table is based on the assumption that the PLLCA55 clock + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be + * clocked to 1.8GHz as well). The table below should be overridden in the board + * DTS based on the PLLCA55 clock frequency. + */ + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + }; + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + opp-212500000 { + opp-hz = /bits/ 64 <212500000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -30,6 +63,8 @@ cpu0: cpu@0 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -38,6 +73,8 @@ cpu1: cpu@100 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -46,6 +83,8 @@ cpu2: cpu@200 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -54,6 +93,8 @@ cpu3: cpu@300 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 {