[v2,5/8] Add micromips to P5600

Commit Message

Aleksandar Rakic Oct. 18, 2024, 1:20 p.m. UTC

Add micromips to P5600.

Cherry-picked d7bf2c2f7f2e03b55c6e9c57eec5c3e6207005a0
from https://github.com/MIPS/gnutools-qemu

Signed-off-by: Faraz Shahbazker <[e-mail]>
Signed-off-by: Matthew Fortune <[e-mail]>
Signed-off-by: Aleksandar Rakic <[e-mail]>
---
 target/mips/cpu-defs.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Aleksandar Rikalo Oct. 19, 2024, 7:45 a.m. UTC | #1

>
> Add micromips to P5600.
>
> Cherry-picked d7bf2c2f7f2e03b55c6e9c57eec5c3e6207005a0
> from https://github.com/MIPS/gnutools-qemu
>
> Signed-off-by: Faraz Shahbazker <[e-mail]>
> Signed-off-by: Matthew Fortune <[e-mail]>
> Signed-off-by: Aleksandar Rakic <[e-mail]>
> ---
>  target/mips/cpu-defs.c.inc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Aleksandar Rikalo <[e-mail]>

-- Aleksandar

Philippe Mathieu-Daudé Oct. 24, 2024, 6:22 p.m. UTC | #2

Hi Aleksandar,

On 18/10/24 10:20, Aleksandar Rakic wrote:
> Add micromips to P5600.
> 
> Cherry-picked d7bf2c2f7f2e03b55c6e9c57eec5c3e6207005a0
> from https://github.com/MIPS/gnutools-qemu
> 
> Signed-off-by: Faraz Shahbazker <[e-mail]>
> Signed-off-by: Matthew Fortune <[e-mail]>
> Signed-off-by: Aleksandar Rakic <[e-mail]>
> ---
>   target/mips/cpu-defs.c.inc | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Please Cc maintainers:

$ ./scripts/get_maintainer.pl -f target/mips/cpu-defs.c.inc
"Philippe Mathieu-Daudé" <[e-mail]> (odd fixer:MIPS TCG CPUs)
Aurelien Jarno <[e-mail]> (reviewer:MIPS TCG CPUs)
Jiaxun Yang <[e-mail]> (reviewer:MIPS TCG CPUs)
Aleksandar Rikalo <[e-mail]> (reviewer:MIPS TCG CPUs)

> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index fbf787d8ce..9428ece220 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -462,7 +462,7 @@ const mips_def_t mips_defs[] =
>           .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
>           .SEGBITS = 32,
>           .PABITS = 40,
> -        .insn_flags = CPU_MIPS32R5,
> +        .insn_flags = CPU_MIPS32R5 | ASE_MICROMIPS,

This doesn't make any sense, if the core has microMIPS then bits 14-15
of CP0_Config3 can't be zeroes (meaning "Only MIPS32 is implemented,
microMIPS not implemented").

Besides, looking at "MIPS32® P5600 Multiprocessing System Software
User’s Manual, Revision 01.60" -> 'Table 2.6 Field Descriptions for
Config3 Register', CP0_Config3_ISA is 0b00, described as:

   Indicates the instruction set availability.
   This bit is always 0 to indicate MIPS32.

What are you trying to achieve, which tests are you running?

>           .mmu_type = MMU_TYPE_R4000,
>       },
>       {

Patch

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index fbf787d8ce..9428ece220 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -462,7 +462,7 @@  const mips_def_t mips_defs[] =
         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
         .SEGBITS = 32,
         .PABITS = 40,
-        .insn_flags = CPU_MIPS32R5,
+        .insn_flags = CPU_MIPS32R5 | ASE_MICROMIPS,
         .mmu_type = MMU_TYPE_R4000,
     },
     {