| Message ID | 20241024223114.785209-4-clinton.a.taylor@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/xe3lpd: ptl display patches | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Clint > Taylor > Sent: Friday, October 25, 2024 4:01 AM > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org > Subject: [PATCH v4 03/11] drm/i915/xe3lpd: Add check to see if edp over type c > is allowed > > From: Suraj Kandpal <suraj.kandpal@intel.com> > > Read PICA register to see if edp over type C is possible and then add the > appropriate tables for it. > > --v2 > -remove bool from intel_encoder have it in runtime_info [Jani] -initialize the > bool in runtime_info init [Jani] -dont abbreviate the bool [Jani] > > --v3 > -Remove useless display version check [Jani] -change the warn on condition > [Jani] -no need for a different function for edp type c check [Jani] -dont add > register in i915_reg [Jani] > > Bspec: 68846 > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> > --- Looks good to me Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy -------------------- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +++ > drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 +++ > drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ > drivers/gpu/drm/i915/display/intel_display_device.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++--- > 5 files changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 8bd5a4d1b735..d05daa7a2b03 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2257,9 +2257,12 @@ intel_c20_pll_tables_get(struct intel_crtc_state > *crtc_state, > struct intel_encoder *encoder) > { > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(crtc_state); > > if (intel_crtc_has_dp_encoder(crtc_state)) { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { > + if (DISPLAY_RUNTIME_INFO(display)- > >edp_typec_support) > + return xe3lpd_c20_dp_edp_tables; > if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) > return xe2hpd_c20_edp_tables; > } > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > index ab3ae110b68f..e8ebb12155a4 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > @@ -363,4 +363,7 @@ > #define HDMI_DIV_MASK REG_GENMASK16(2, 0) > #define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) > > +#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) > +#define EDP_ON_TYPEC REG_BIT(31) > + > #endif /* __INTEL_CX0_REG_DEFS_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c > b/drivers/gpu/drm/i915/display/intel_display_device.c > index aa22189e3853..949838308ec9 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -9,6 +9,7 @@ > > #include "i915_drv.h" > #include "i915_reg.h" > +#include "intel_cx0_phy_regs.h" > #include "intel_de.h" > #include "intel_display.h" > #include "intel_display_device.h" > @@ -1685,6 +1686,10 @@ static void > __intel_display_device_info_runtime_init(struct drm_i915_private *i9 > } > } > > + if (DISPLAY_VER(i915) >= 30) > + display_runtime->edp_typec_support = > + intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & > EDP_ON_TYPEC; > + > display_runtime->rawclk_freq = intel_read_rawclk(display); > drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime- > >rawclk_freq); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h > b/drivers/gpu/drm/i915/display/intel_display_device.h > index 071a36b51f79..410f8b33a8a1 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > @@ -232,6 +232,7 @@ struct intel_display_runtime_info { > bool has_hdcp; > bool has_dmc; > bool has_dsc; > + bool edp_typec_support; > }; > > struct intel_display_device_info { > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 7e29619ba040..9f015b530289 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6441,10 +6441,11 @@ intel_dp_init_connector(struct intel_digital_port > *dig_port, > > if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) { > /* > - * Currently we don't support eDP on TypeC ports, although in > - * theory it could work on TypeC legacy ports. > + * Currently we don't support eDP on TypeC ports for > DISPLAY_VER < 30, > + * although in theory it could work on TypeC legacy ports. > */ > - drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder)); > + drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) && > + DISPLAY_VER(dev_priv) < 30); > type = DRM_MODE_CONNECTOR_eDP; > intel_encoder->type = INTEL_OUTPUT_EDP; > > -- > 2.25.1
On Thu, 24 Oct 2024, Clint Taylor <clinton.a.taylor@intel.com> wrote: > From: Suraj Kandpal <suraj.kandpal@intel.com> > > Read PICA register to see if edp over type C is possible and then > add the appropriate tables for it. > > --v2 > -remove bool from intel_encoder have it in runtime_info [Jani] > -initialize the bool in runtime_info init [Jani] > -dont abbreviate the bool [Jani] > > --v3 > -Remove useless display version check [Jani] > -change the warn on condition [Jani] > -no need for a different function for edp type c check [Jani] > -dont add register in i915_reg [Jani] > > Bspec: 68846 > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +++ > drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 +++ > drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ > drivers/gpu/drm/i915/display/intel_display_device.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++--- > 5 files changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 8bd5a4d1b735..d05daa7a2b03 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2257,9 +2257,12 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, > struct intel_encoder *encoder) > { > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + struct intel_display *display = to_intel_display(crtc_state); > > if (intel_crtc_has_dp_encoder(crtc_state)) { > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { > + if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support) > + return xe3lpd_c20_dp_edp_tables; > if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) > return xe2hpd_c20_edp_tables; > } > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > index ab3ae110b68f..e8ebb12155a4 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > @@ -363,4 +363,7 @@ > #define HDMI_DIV_MASK REG_GENMASK16(2, 0) > #define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) > > +#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) > +#define EDP_ON_TYPEC REG_BIT(31) > + > #endif /* __INTEL_CX0_REG_DEFS_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index aa22189e3853..949838308ec9 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -9,6 +9,7 @@ > > #include "i915_drv.h" > #include "i915_reg.h" > +#include "intel_cx0_phy_regs.h" > #include "intel_de.h" > #include "intel_display.h" > #include "intel_display_device.h" > @@ -1685,6 +1686,10 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 > } > } > > + if (DISPLAY_VER(i915) >= 30) > + display_runtime->edp_typec_support = > + intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC; > + > display_runtime->rawclk_freq = intel_read_rawclk(display); > drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h > index 071a36b51f79..410f8b33a8a1 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > @@ -232,6 +232,7 @@ struct intel_display_runtime_info { > bool has_hdcp; > bool has_dmc; > bool has_dsc; > + bool edp_typec_support; > }; > > struct intel_display_device_info { > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 7e29619ba040..9f015b530289 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6441,10 +6441,11 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, > > if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) { > /* > - * Currently we don't support eDP on TypeC ports, although in > - * theory it could work on TypeC legacy ports. > + * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, > + * although in theory it could work on TypeC legacy ports. > */ > - drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder)); > + drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) && > + DISPLAY_VER(dev_priv) < 30); > type = DRM_MODE_CONNECTOR_eDP; > intel_encoder->type = INTEL_OUTPUT_EDP;
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 8bd5a4d1b735..d05daa7a2b03 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2257,9 +2257,12 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(crtc_state); if (intel_crtc_has_dp_encoder(crtc_state)) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { + if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support) + return xe3lpd_c20_dp_edp_tables; if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) return xe2hpd_c20_edp_tables; } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index ab3ae110b68f..e8ebb12155a4 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -363,4 +363,7 @@ #define HDMI_DIV_MASK REG_GENMASK16(2, 0) #define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) +#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) +#define EDP_ON_TYPEC REG_BIT(31) + #endif /* __INTEL_CX0_REG_DEFS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index aa22189e3853..949838308ec9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "intel_cx0_phy_regs.h" #include "intel_de.h" #include "intel_display.h" #include "intel_display_device.h" @@ -1685,6 +1686,10 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 } } + if (DISPLAY_VER(i915) >= 30) + display_runtime->edp_typec_support = + intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC; + display_runtime->rawclk_freq = intel_read_rawclk(display); drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 071a36b51f79..410f8b33a8a1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -232,6 +232,7 @@ struct intel_display_runtime_info { bool has_hdcp; bool has_dmc; bool has_dsc; + bool edp_typec_support; }; struct intel_display_device_info { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7e29619ba040..9f015b530289 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6441,10 +6441,11 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) { /* - * Currently we don't support eDP on TypeC ports, although in - * theory it could work on TypeC legacy ports. + * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, + * although in theory it could work on TypeC legacy ports. */ - drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder)); + drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) && + DISPLAY_VER(dev_priv) < 30); type = DRM_MODE_CONNECTOR_eDP; intel_encoder->type = INTEL_OUTPUT_EDP;