diff mbox series

[v3,4/4] arm64: dts: qcom: qcs615: add the APPS SMMU node

Message ID 20241025030732.29743-5-quic_qqzhou@quicinc.com (mailing list archive)
State New
Headers show
Series Add support for APPS SMMU on QCS615 | expand

Commit Message

Qingqing Zhou Oct. 25, 2024, 3:07 a.m. UTC 
Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
to limit DMA address range to 36bit width to align with system
architecture.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

Comments

Konrad Dybcio Oct. 25, 2024, 8:54 a.m. UTC | #1 
On 25.10.2024 5:07 AM, Qingqing Zhou wrote:
> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
> to limit DMA address range to 36bit width to align with system
> architecture.
> 
> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
> ---

You probably also want to mark it `dma-coherent` (see e.g.
x1e80100.dtsi)

Konrad
Dmitry Baryshkov Oct. 25, 2024, 11:06 a.m. UTC | #2 
On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote:
> On 25.10.2024 5:07 AM, Qingqing Zhou wrote:
> > Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
> > to limit DMA address range to 36bit width to align with system
> > architecture.
> > 
> > Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
> > ---
> 
> You probably also want to mark it `dma-coherent` (see e.g.
> x1e80100.dtsi)

Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't
marked as such.
Konrad Dybcio Oct. 25, 2024, 4:45 p.m. UTC | #3 
On 25.10.2024 1:06 PM, Dmitry Baryshkov wrote:
> On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote:
>> On 25.10.2024 5:07 AM, Qingqing Zhou wrote:
>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
>>> to limit DMA address range to 36bit width to align with system
>>> architecture.
>>>
>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
>>> ---
>>
>> You probably also want to mark it `dma-coherent` (see e.g.
>> x1e80100.dtsi)
> 
> Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't
> marked as such.

I don't think I have any documentation on this, so.. one way to find out!

Konrad
Dmitry Baryshkov Oct. 26, 2024, 6:18 p.m. UTC | #4 
On Fri, Oct 25, 2024 at 06:45:01PM +0200, Konrad Dybcio wrote:
> On 25.10.2024 1:06 PM, Dmitry Baryshkov wrote:
> > On Fri, Oct 25, 2024 at 10:54:24AM +0200, Konrad Dybcio wrote:
> >> On 25.10.2024 5:07 AM, Qingqing Zhou wrote:
> >>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
> >>> to limit DMA address range to 36bit width to align with system
> >>> architecture.
> >>>
> >>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
> >>> ---
> >>
> >> You probably also want to mark it `dma-coherent` (see e.g.
> >> x1e80100.dtsi)
> > 
> > Is it? I don't think SM6150 had dma-coherent SMMU, at least it wasn't
> > marked as such.
> 
> I don't think I have any documentation on this, so.. one way to find out!

I don't have qcs615 at hand, so a purely theoretical question. But how
should it break if we mark it as dma-coherent, while it is not?
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 027c5125f36b..38428e4537b7 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -379,6 +379,7 @@ 
 	soc: soc@0 {
 		compatible = "simple-bus";
 		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 
@@ -524,6 +525,79 @@ 
 			reg = <0x0 0x0c3f0000 0x0 0x400>;
 		};
 
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x80000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		intc: interrupt-controller@17a00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */