diff mbox series

[v2] arm64: dts: ti: k3-j7200: Fix register map for main domain pmx

Message ID 20240926102533.398139-1-a-limaye@ti.com (mailing list archive)
State New, archived
Headers show
Series [v2] arm64: dts: ti: k3-j7200: Fix register map for main domain pmx | expand

Commit Message

Aniket Limaye Sept. 26, 2024, 10:25 a.m. UTC
From: Jared McArthur <j-mcarthur@ti.com>

Commit 0d0a0b441346 ("arm64: dts: ti: k3-j7200: fix main pinmux
range") split the main_pmx0 into two nodes: main_pmx0 and main_pmx1
due to a non-addressable region, but incorrectly represented the
ranges. As a result, the memory map for the pinctrl is incorrect. Fix
this by introducing the correct ranges.

The ranges are taken from the J7200 TRM [1] (Table 5-695. CTRL_MMR0
Registers).

Padconfig starting addresses and ranges:
-  0 to 66: 0x11c000, 0x10c
-       68: 0x11c110, 0x004
- 71 to 73: 0x11c11c, 0x00c
- 89 to 90: 0x11c164, 0x008

The datasheet [2] doesn't contain PADCONFIG63 (Table 6-106. Pin
Multiplexing), but the pin is necessary for enabling the MMC1 CLKLP
pad loopback and should be included in the pinmux register map.

Due to the change in pinmux node addresses, change the pinmux node for
the USB0_DRVVBUS pin to main_pmx2. The offset has not changed since the
new main_pmx2 node has the same base address and range as the original
main_pmx1 node. All other pinmuxing done within J7200 dts or dtso files
only uses main_pmx0 which has not changed.

[1] https://www.ti.com/lit/pdf/spruiu1
[2] https://www.ti.com/lit/gpn/dra821u

Fixes: 0d0a0b441346 ("arm64: dts: ti: k3-j7200: fix main pinmux range")
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
---
Changes in v2:
- Explains why PADCONFIG63 is included in the pinmux ranges when it
  doesn't appear in the datasheet.

* Nishanth
- Use cannonical links in commit msg for the TRM and Datasheet
- Explains the reason for the offset not changing for the USB0_DRVVBUS
  pin and why there are no changes to other pins.

- Link to v1: https://lore.kernel.org/all/20240829071208.2172825-1-a-limaye@ti.com/
---
 .../dts/ti/k3-j7200-common-proc-board.dts     |  2 +-
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 22 +++++++++++++++++--
 2 files changed, 21 insertions(+), 3 deletions(-)

Comments

Vaishnav Achath Oct. 14, 2024, 6:26 a.m. UTC | #1
Hi Aniket, Jared,


On 26/09/24 15:55, Aniket Limaye wrote:
> From: Jared McArthur <j-mcarthur@ti.com>
> 
> Commit 0d0a0b441346 ("arm64: dts: ti: k3-j7200: fix main pinmux
> range") split the main_pmx0 into two nodes: main_pmx0 and main_pmx1
> due to a non-addressable region, but incorrectly represented the
> ranges. As a result, the memory map for the pinctrl is incorrect. Fix
> this by introducing the correct ranges.
> 
> The ranges are taken from the J7200 TRM [1] (Table 5-695. CTRL_MMR0
> Registers).
> 
> Padconfig starting addresses and ranges:
> -  0 to 66: 0x11c000, 0x10c
> -       68: 0x11c110, 0x004
> - 71 to 73: 0x11c11c, 0x00c
> - 89 to 90: 0x11c164, 0x008
> 
> The datasheet [2] doesn't contain PADCONFIG63 (Table 6-106. Pin
> Multiplexing), but the pin is necessary for enabling the MMC1 CLKLP
> pad loopback and should be included in the pinmux register map.
> 
> Due to the change in pinmux node addresses, change the pinmux node for
> the USB0_DRVVBUS pin to main_pmx2. The offset has not changed since the
> new main_pmx2 node has the same base address and range as the original
> main_pmx1 node. All other pinmuxing done within J7200 dts or dtso files
> only uses main_pmx0 which has not changed.
> 
> [1] https://www.ti.com/lit/pdf/spruiu1
> [2] https://www.ti.com/lit/gpn/dra821u
> 
> Fixes: 0d0a0b441346 ("arm64: dts: ti: k3-j7200: fix main pinmux range")
> Signed-off-by: Aniket Limaye <a-limaye@ti.com>
> Signed-off-by: Jared McArthur <j-mcarthur@ti.com>

Thank you for the patch.

Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>

> ---
> Changes in v2:
> - Explains why PADCONFIG63 is included in the pinmux ranges when it
>    doesn't appear in the datasheet.
> 
> * Nishanth
> - Use cannonical links in commit msg for the TRM and Datasheet
> - Explains the reason for the offset not changing for the USB0_DRVVBUS
>    pin and why there are no changes to other pins.
> 
> - Link to v1: https://lore.kernel.org/all/20240829071208.2172825-1-a-limaye@ti.com/
> ---
>   .../dts/ti/k3-j7200-common-proc-board.dts     |  2 +-
>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 22 +++++++++++++++++--
>   2 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 6593c5da82c06..df39f2b1ff6ba 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -254,7 +254,7 @@ J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */
>   	};
>   };
>   
> -&main_pmx1 {
> +&main_pmx2 {
>   	main_usbss0_pins_default: main-usbss0-default-pins {
>   		pinctrl-single,pins = <
>   			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 9386bf3ef9f68..41adfa64418d0 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -426,10 +426,28 @@ main_pmx0: pinctrl@11c000 {
>   		pinctrl-single,function-mask = <0xffffffff>;
>   	};
>   
> -	main_pmx1: pinctrl@11c11c {
> +	main_pmx1: pinctrl@11c110 {
>   		compatible = "ti,j7200-padconf", "pinctrl-single";
>   		/* Proxy 0 addressing */
> -		reg = <0x00 0x11c11c 0x00 0xc>;
> +		reg = <0x00 0x11c110 0x00 0x004>;
> +		#pinctrl-cells = <1>;
> +		pinctrl-single,register-width = <32>;
> +		pinctrl-single,function-mask = <0xffffffff>;
> +	};
> +
> +	main_pmx2: pinctrl@11c11c {
> +		compatible = "ti,j7200-padconf", "pinctrl-single";
> +		/* Proxy 0 addressing */
> +		reg = <0x00 0x11c11c 0x00 0x00c>;
> +		#pinctrl-cells = <1>;
> +		pinctrl-single,register-width = <32>;
> +		pinctrl-single,function-mask = <0xffffffff>;
> +	};
> +
> +	main_pmx3: pinctrl@11c164 {
> +		compatible = "ti,j7200-padconf", "pinctrl-single";
> +		/* Proxy 0 addressing */
> +		reg = <0x00 0x11c164 0x00 0x008>;
>   		#pinctrl-cells = <1>;
>   		pinctrl-single,register-width = <32>;
>   		pinctrl-single,function-mask = <0xffffffff>;
Vignesh Raghavendra Oct. 30, 2024, 4:52 a.m. UTC | #2
Hi Aniket Limaye,

On Thu, 26 Sep 2024 15:55:33 +0530, Aniket Limaye wrote:
> Commit 0d0a0b441346 ("arm64: dts: ti: k3-j7200: fix main pinmux
> range") split the main_pmx0 into two nodes: main_pmx0 and main_pmx1
> due to a non-addressable region, but incorrectly represented the
> ranges. As a result, the memory map for the pinctrl is incorrect. Fix
> this by introducing the correct ranges.
> 
> The ranges are taken from the J7200 TRM [1] (Table 5-695. CTRL_MMR0
> Registers).
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/1] arm64: dts: ti: k3-j7200: Fix register map for main domain pmx
      commit: b7af8b4acb3e08c710cd48f098ce8cd07cf43a1e

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6593c5da82c06..df39f2b1ff6ba 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -254,7 +254,7 @@  J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */
 	};
 };
 
-&main_pmx1 {
+&main_pmx2 {
 	main_usbss0_pins_default: main-usbss0-default-pins {
 		pinctrl-single,pins = <
 			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 9386bf3ef9f68..41adfa64418d0 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -426,10 +426,28 @@  main_pmx0: pinctrl@11c000 {
 		pinctrl-single,function-mask = <0xffffffff>;
 	};
 
-	main_pmx1: pinctrl@11c11c {
+	main_pmx1: pinctrl@11c110 {
 		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
-		reg = <0x00 0x11c11c 0x00 0xc>;
+		reg = <0x00 0x11c110 0x00 0x004>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+	};
+
+	main_pmx2: pinctrl@11c11c {
+		compatible = "ti,j7200-padconf", "pinctrl-single";
+		/* Proxy 0 addressing */
+		reg = <0x00 0x11c11c 0x00 0x00c>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+	};
+
+	main_pmx3: pinctrl@11c164 {
+		compatible = "ti,j7200-padconf", "pinctrl-single";
+		/* Proxy 0 addressing */
+		reg = <0x00 0x11c164 0x00 0x008>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
 		pinctrl-single,function-mask = <0xffffffff>;