| Message ID | 20241030-v6-12-topic-socfpga-agilex5-v1-4-b2b67780e60e@pengutronix.de (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | ARM64: dts: intel: agilex5: add nodes and new board | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
> +&gmac2 { > + status = "okay"; > + phy-mode = "rgmii-id"; > + phy-handle = <&emac2_phy0>; > + > + max-frame-size = <9000>; > + > + mdio0 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + emac2_phy0: ethernet-phy@1 { > + reg = <0x1>; > + adi,rx-internal-delay-ps = <2000>; > + adi,tx-internal-delay-ps = <2000>; You have rgmii-id and 2000ps delay? Are these two lines actually required? Andrew
On 30/10/2024 13:10, Steffen Trumtrar wrote: > The Arrow AXE5-Eagle is an Intel Agilex5 SoCFPGA based board with: > > - 1x PCIe Gen4.0 edge connector > - 4-port USB HUB > - 2x 1Gb Ethernet > - microSD > - HDMI output > - 2x 10Gb SFP+ cages > > As most devices aren't supported mainline yet, this is only the initial > support for the board. > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > --- > arch/arm64/boot/dts/intel/Makefile | 1 + > .../boot/dts/intel/socfpga_agilex5_axe5_eagle.dts | 146 +++++++++++++++++++++ > 2 files changed, 147 insertions(+) > > diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile > index d39cfb723f5b6674a821dfdafb21b12668bb1e0e..3e87d548c532b1a9e38f4489c037c5c4db3a50b8 100644 > --- a/arch/arm64/boot/dts/intel/Makefile > +++ b/arch/arm64/boot/dts/intel/Makefile > @@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ > socfpga_agilex_socdk.dtb \ > socfpga_agilex_socdk_nand.dtb \ > socfpga_agilex5_socdk.dtb \ > + socfpga_agilex5_axe5_eagle.dtb \ > socfpga_n5x_socdk.dtb > dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts > new file mode 100644 > index 0000000000000000000000000000000000000000..bd5bd8f680c9ade49ac174108beed6828c5a925d > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts > @@ -0,0 +1,146 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2024, Arrow Electronics, Inc. > + */ > +#include "socfpga_agilex5.dtsi" > + > +/ { > + model = "SoCFPGA Agilex5 Arrow AXE5-Eagle"; > + compatible = "arrow,socfpga-agilex5-axe5-eagle", "intel,socfpga-agilex"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + leds { > + compatible = "gpio-leds"; > + > + hps0 { It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). I think you are sending some downstream code. I am not sure if Agilex was corrected, but usually starting from upstream code is better choice. > + label = "hps_led0"; > + gpios = <&porta 6 GPIO_ACTIVE_HIGH>; > + }; > + > + hps1 { > + label = "hps_led1"; > + gpios = <&porta 7 GPIO_ACTIVE_HIGH>; > + }; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + > + hps_sw0 { So this is copy of old arm stuff. Still needs to be fixed, see DTS coding style. It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). ... > +&i2c1 { > + status = "okay"; > + > + tca9544@70 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "nxp,pca9544"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x70>; > + status = "okay"; > + }; Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index d39cfb723f5b6674a821dfdafb21b12668bb1e0e..3e87d548c532b1a9e38f4489c037c5c4db3a50b8 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_agilex5_socdk.dtb \ + socfpga_agilex5_axe5_eagle.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts new file mode 100644 index 0000000000000000000000000000000000000000..bd5bd8f680c9ade49ac174108beed6828c5a925d --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_axe5_eagle.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Arrow Electronics, Inc. + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 Arrow AXE5-Eagle"; + compatible = "arrow,socfpga-agilex5-axe5-eagle", "intel,socfpga-agilex"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + hps0 { + label = "hps_led0"; + gpios = <&porta 6 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&porta 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_sw0 { + label = "hps_sw0"; + gpios = <&porta 10 0>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; + }; + + hps_sw1 { + label = "hps_sw1"; + gpios = <&porta 1 0>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; + }; + + hps_pb0 { + label = "hps_pb0"; + gpios = <&porta 8 1>; + linux,code = <187>; /* KEY_F17 */ + }; + + hps_pb1 { + label = "hps_pb1"; + gpios = <&porta 9 1>; + linux,code = <188>; /* KEY_F18 */ + }; + }; + + vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3_3: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + emac2_phy0: ethernet-phy@1 { + reg = <0x1>; + adi,rx-internal-delay-ps = <2000>; + adi,tx-internal-delay-ps = <2000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tca9544@70 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + status = "okay"; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; + +&uart0 { + status = "okay"; +};
The Arrow AXE5-Eagle is an Intel Agilex5 SoCFPGA based board with: - 1x PCIe Gen4.0 edge connector - 4-port USB HUB - 2x 1Gb Ethernet - microSD - HDMI output - 2x 10Gb SFP+ cages As most devices aren't supported mainline yet, this is only the initial support for the board. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> --- arch/arm64/boot/dts/intel/Makefile | 1 + .../boot/dts/intel/socfpga_agilex5_axe5_eagle.dts | 146 +++++++++++++++++++++ 2 files changed, 147 insertions(+)