| Message ID | 9002a58daa1b2983f39815b748ee9d2f8dcc4829.1730366936.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | ARM: dts: am335x-bone-common: Increase MDIO reset deassert delay to 50ms | expand |
On 31/10/2024 11:29, Geert Uytterhoeven wrote: > Commit b9bf5612610aa7e3 ("ARM: dts: am335x-bone-common: Increase MDIO > reset deassert time") already increased the MDIO reset deassert delay > from 6.5 to 13 ms, but this may still cause Ethernet PHY probe failures: > > SMSC LAN8710/LAN8720 4a101000.mdio:00: probe with driver SMSC LAN8710/LAN8720 failed with error -5 > > On BeagleBone Black Rev. C3, ETH_RESETn is controlled by an open-drain > AND gate. It is pulled high by a 10K resistor, and has a 4.7µF > capacitor to ground, giving an RC time constant of 47ms. As it takes > 0.7RC to charge the capacitor above the threshold voltage of a CMOS > input (VDD/2), the delay should be at least 33ms. Considering the > typical tolerance of 20% on capacitors, 40ms would be safer. Add an > additional safety margin and settle for 50ms. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Roger Quadros <rogerq@kernel.org>
diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi index a0fb431aec8411d8..212d7f867f8786af 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi @@ -409,7 +409,7 @@ ethphy0: ethernet-phy@0 { /* Support GPIO reset on revision C3 boards */ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; reset-assert-us = <300>; - reset-deassert-us = <13000>; + reset-deassert-us = <50000>; }; };
Commit b9bf5612610aa7e3 ("ARM: dts: am335x-bone-common: Increase MDIO reset deassert time") already increased the MDIO reset deassert delay from 6.5 to 13 ms, but this may still cause Ethernet PHY probe failures: SMSC LAN8710/LAN8720 4a101000.mdio:00: probe with driver SMSC LAN8710/LAN8720 failed with error -5 On BeagleBone Black Rev. C3, ETH_RESETn is controlled by an open-drain AND gate. It is pulled high by a 10K resistor, and has a 4.7µF capacitor to ground, giving an RC time constant of 47ms. As it takes 0.7RC to charge the capacitor above the threshold voltage of a CMOS input (VDD/2), the delay should be at least 33ms. Considering the typical tolerance of 20% on capacitors, 40ms would be safer. Add an additional safety margin and settle for 50ms. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)