| Message ID | 20241105-dcd-type2-upstream-v6-5-85c7fa2140fe@intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | DCD: Add support for Dynamic Capacity Devices (DCD) | expand |
On Tue, 05 Nov 2024 12:38:27 -0600 Ira Weiny <ira.weiny@intel.com> wrote: > Additional DCD functionality is being added to this call which will be > simplified by the use of guard() with the cxl_dpa_rwsem. > > Convert the function to use guard() prior to adding DCD functionality. > > Suggested-by: Jonathan Cameron <Jonathan.Cameron@Huawei.com> > Signed-off-by: Ira Weiny <ira.weiny@intel.com> You missed some RBs from v5 and I don't think this changed. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Davidlohr also gave one. > --- > drivers/cxl/core/hdm.c | 21 ++++++--------------- > 1 file changed, 6 insertions(+), 15 deletions(-) > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 3df10517a3278f228c7535fcbdb607d7b75bc879..463ba2669cea55194e2be2c26d02af75dde8d145 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -424,7 +424,6 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, > struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); > struct cxl_dev_state *cxlds = cxlmd->cxlds; > struct device *dev = &cxled->cxld.dev; > - int rc; > > switch (mode) { > case CXL_DECODER_RAM: > @@ -435,11 +434,9 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, > return -EINVAL; > } > > - down_write(&cxl_dpa_rwsem); > - if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) { > - rc = -EBUSY; > - goto out; > - } > + guard(rwsem_write)(&cxl_dpa_rwsem); > + if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) > + return -EBUSY; > > /* > * Only allow modes that are supported by the current partition > @@ -447,21 +444,15 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, > */ > if (mode == CXL_DECODER_PMEM && !resource_size(&cxlds->pmem_res)) { > dev_dbg(dev, "no available pmem capacity\n"); > - rc = -ENXIO; > - goto out; > + return -ENXIO; > } > if (mode == CXL_DECODER_RAM && !resource_size(&cxlds->ram_res)) { > dev_dbg(dev, "no available ram capacity\n"); > - rc = -ENXIO; > - goto out; > + return -ENXIO; > } > > cxled->mode = mode; > - rc = 0; > -out: > - up_write(&cxl_dpa_rwsem); > - > - return rc; > + return 0; > } > > int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) >
Jonathan Cameron wrote: > On Tue, 05 Nov 2024 12:38:27 -0600 > Ira Weiny <ira.weiny@intel.com> wrote: > > > Additional DCD functionality is being added to this call which will be > > simplified by the use of guard() with the cxl_dpa_rwsem. > > > > Convert the function to use guard() prior to adding DCD functionality. > > > > Suggested-by: Jonathan Cameron <Jonathan.Cameron@Huawei.com> > > Signed-off-by: Ira Weiny <ira.weiny@intel.com> > > You missed some RBs from v5 and I don't think this changed. > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > Davidlohr also gave one. Apologies. I've been using b4 trailers to pick them up. It looks like it worked this time just fine. :-/ Ira
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 3df10517a3278f228c7535fcbdb607d7b75bc879..463ba2669cea55194e2be2c26d02af75dde8d145 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -424,7 +424,6 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); struct cxl_dev_state *cxlds = cxlmd->cxlds; struct device *dev = &cxled->cxld.dev; - int rc; switch (mode) { case CXL_DECODER_RAM: @@ -435,11 +434,9 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, return -EINVAL; } - down_write(&cxl_dpa_rwsem); - if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) { - rc = -EBUSY; - goto out; - } + guard(rwsem_write)(&cxl_dpa_rwsem); + if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) + return -EBUSY; /* * Only allow modes that are supported by the current partition @@ -447,21 +444,15 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, */ if (mode == CXL_DECODER_PMEM && !resource_size(&cxlds->pmem_res)) { dev_dbg(dev, "no available pmem capacity\n"); - rc = -ENXIO; - goto out; + return -ENXIO; } if (mode == CXL_DECODER_RAM && !resource_size(&cxlds->ram_res)) { dev_dbg(dev, "no available ram capacity\n"); - rc = -ENXIO; - goto out; + return -ENXIO; } cxled->mode = mode; - rc = 0; -out: - up_write(&cxl_dpa_rwsem); - - return rc; + return 0; } int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size)
Additional DCD functionality is being added to this call which will be simplified by the use of guard() with the cxl_dpa_rwsem. Convert the function to use guard() prior to adding DCD functionality. Suggested-by: Jonathan Cameron <Jonathan.Cameron@Huawei.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> --- drivers/cxl/core/hdm.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-)