| Message ID | 20241107041016.40800-1-alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
On Thu, 7 Nov 2024 at 04:11, Alistair Francis <alistair23@gmail.com> wrote: > > The following changes since commit 63dc36944383f70f1c7a20f6104966d8560300fa: > > Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging (2024-11-06 17:28:45 +0000) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241107 > > for you to fetch changes up to 27652f9ca9d831c67dd447346c6ee953669255f0: > > tests/functional: Convert the RV32-on-RV64 riscv test (2024-11-07 13:12:58 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 9.2 > > * Fix broken SiFive UART on big endian hosts > * Fix IOMMU Coverity issues > * Improve the performance of vector unit-stride/whole register ld/st instructions > * Update kvm exts to Linux v6.11 > * Convert the RV32-on-RV64 riscv test > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2 for any user-visible changes. -- PMM
The following changes since commit 63dc36944383f70f1c7a20f6104966d8560300fa: Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging (2024-11-06 17:28:45 +0000) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241107 for you to fetch changes up to 27652f9ca9d831c67dd447346c6ee953669255f0: tests/functional: Convert the RV32-on-RV64 riscv test (2024-11-07 13:12:58 +1000) ---------------------------------------------------------------- RISC-V PR for 9.2 * Fix broken SiFive UART on big endian hosts * Fix IOMMU Coverity issues * Improve the performance of vector unit-stride/whole register ld/st instructions * Update kvm exts to Linux v6.11 * Convert the RV32-on-RV64 riscv test ---------------------------------------------------------------- Daniel Henrique Barboza (2): hw/riscv/riscv-iommu: change 'depth' to int hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check Max Chou (7): target/riscv: Set vdata.vm field for vector load/store whole register instructions target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions target/riscv: Inline unit-stride ld/st and corresponding functions for performance Quan Zhou (1): target/riscv/kvm: Update kvm exts to Linux v6.11 Thomas Huth (2): hw/char/sifive_uart: Fix broken UART on big endian hosts tests/functional: Convert the RV32-on-RV64 riscv test hw/char/sifive_uart.c | 3 +- hw/riscv/riscv-iommu.c | 4 +- target/riscv/kvm/kvm-cpu.c | 7 + target/riscv/vector_helper.c | 598 +++++++++++++++++++++----------- target/riscv/insn_trans/trans_rvv.c.inc | 3 + tests/avocado/tuxrun_baselines.py | 16 - tests/functional/test_riscv64_tuxrun.py | 13 + 7 files changed, 424 insertions(+), 220 deletions(-)