diff mbox series

drm/i915/display: Add WA_14018221282

Message ID 20241108080109.3049672-1-nemesa.garg@intel.com (mailing list archive)
State New
Headers show
Series drm/i915/display: Add WA_14018221282 | expand

Commit Message

Garg, Nemesa Nov. 8, 2024, 8:01 a.m. UTC 
It was observed that the first write to DKL DP Mode register
was not taking effect, hence rewrite this register.

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Golani, Mitulkumar Ajitkumar Nov. 8, 2024, 8:16 a.m. UTC | #1 
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Nemesa Garg
> Sent: 08 November 2024 13:31
> To: intel-gfx@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH] drm/i915/display: Add WA_14018221282
> 
> It was observed that the first write to DKL DP Mode register was not taking
> effect, hence rewrite this register.
> 
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 769bd1f26db2..16a1d18f3aa1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2104,6 +2104,16 @@ void
> intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
>  	encoder->disable_clock(encoder);
>  }
> 
> +static void
> +tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port
> tc_port,

1. I recommend, Need to think on naming here, as doesn't clarify on anything.
2. Also adding on thought to have pre-check of return if values are already updated.

> +		   u32 ln0, u32 ln1)
> +{
> +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
> ln0);
> +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
> ln1); }
> +
>  static void
>  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  		       const struct intel_crtc_state *crtc_state) @@ -2185,6
> +2195,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  	if (DISPLAY_VER(dev_priv) >= 12) {
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
> ln0);
>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
> ln1);
> +		 /* WA_14018221282 */
> +		if (DISPLAY_VER(dev_priv) == 12)
> +			tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);

Always use the display local var when possible. DISPLAY_VER(display)

> +
>  	} else {
>  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
>  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
> --
> 2.25.1
Garg, Nemesa Nov. 8, 2024, 9:02 a.m. UTC | #2 
> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Friday, November 8, 2024 1:47 PM
> To: Garg, Nemesa <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: RE: [PATCH] drm/i915/display: Add WA_14018221282
> 
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Nemesa Garg
> > Sent: 08 November 2024 13:31
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
> > Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > Subject: [PATCH] drm/i915/display: Add WA_14018221282
> >
> > It was observed that the first write to DKL DP Mode register was not
> > taking effect, hence rewrite this register.
> >
> > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> > Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 769bd1f26db2..16a1d18f3aa1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2104,6 +2104,16 @@ void
> > intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> >  	encoder->disable_clock(encoder);
> >  }
> >
> > +static void
> > +tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port
> > tc_port,
> 
> 1. I recommend, Need to think on naming here, as doesn't clarify on anything.
Sure will rename it.
> 2. Also adding on thought to have pre-check of return if values are already
> updated.
I guess return is not required because before writing the values I am checking whether
values are updated or not, then only writing the values.
> 
> > +		   u32 ln0, u32 ln1)
> > +{
> > +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
> > +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
> > ln0);
> > +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
> > +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
> > ln1); }
> > +
> >  static void
> >  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
> >  		       const struct intel_crtc_state *crtc_state) @@ -2185,6
> > +2195,10 @@ icl_program_mg_dp_mode(struct intel_digital_port
> > +*dig_port,
> >  	if (DISPLAY_VER(dev_priv) >= 12) {
> >  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
> >  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
> > +		 /* WA_14018221282 */
> > +		if (DISPLAY_VER(dev_priv) == 12)
> > +			tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);
> 
> Always use the display local var when possible. DISPLAY_VER(display)
Sure will do.
> 
> > +
> >  	} else {
> >  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
> >  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
> > --
> > 2.25.1
Jani Nikula Nov. 8, 2024, 9:32 a.m. UTC | #3 
On Fri, 08 Nov 2024, "Golani, Mitulkumar Ajitkumar" <mitulkumar.ajitkumar.golani@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
>> Nemesa Garg
>> Sent: 08 November 2024 13:31
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Garg, Nemesa <nemesa.garg@intel.com>; Kulkarni@freedesktop.org;
>> Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> Subject: [PATCH] drm/i915/display: Add WA_14018221282
>> 
>> It was observed that the first write to DKL DP Mode register was not taking
>> effect, hence rewrite this register.
>> 
>> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
>> Signed-off-by: Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 769bd1f26db2..16a1d18f3aa1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2104,6 +2104,16 @@ void
>> intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
>>  	encoder->disable_clock(encoder);
>>  }
>> 
>> +static void
>> +tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port
>> tc_port,
>
> 1. I recommend, Need to think on naming here, as doesn't clarify on anything.

Yes please everyone stop with the madness of naming functions
bla_bla_wa_124235432().

BR,
Jani.


> 2. Also adding on thought to have pre-check of return if values are already updated.
>
>> +		   u32 ln0, u32 ln1)
>> +{
>> +	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
>> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
>> ln0);
>> +	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
>> +		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
>> ln1); }
>> +
>>  static void
>>  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>>  		       const struct intel_crtc_state *crtc_state) @@ -2185,6
>> +2195,10 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>>  	if (DISPLAY_VER(dev_priv) >= 12) {
>>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0),
>> ln0);
>>  		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1),
>> ln1);
>> +		 /* WA_14018221282 */
>> +		if (DISPLAY_VER(dev_priv) == 12)
>> +			tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);
>
> Always use the display local var when possible. DISPLAY_VER(display)
>
>> +
>>  	} else {
>>  		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
>>  		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
>> --
>> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 769bd1f26db2..16a1d18f3aa1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2104,6 +2104,16 @@  void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 	encoder->disable_clock(encoder);
 }
 
+static void
+tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port tc_port,
+		   u32 ln0, u32 ln1)
+{
+	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
+		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+}
+
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
@@ -2185,6 +2195,10 @@  icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
 		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+		 /* WA_14018221282 */
+		if (DISPLAY_VER(dev_priv) == 12)
+			tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);
+
 	} else {
 		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
 		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);