| Message ID | 20241108-tcon_fix-v1-1-616218cc0d5f@jookia.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/sun4i: Workaround TCON TOP conflict between DE0 and DE1 | expand |
On Fri, 08 Nov 2024 12:40:16 +1100 John Watts <contact@jookia.org> wrote: Hi John, thanks for taking care and sending a patch! > On the D1 and T113 the TCON TOP cannot handle setting both DEs to a > single output, even if the outputs are disabled. As a workaround assign > DE1 to TVE0 by default. Can you say *why* this patch is needed? Is there something broken that needs fixing? Where does this show and why wasn't this a problem before? > A full fix for this would include logic that makes sure both DEs never > share the same output. To be honest, given the isolation on this patch, I'd rather wait for this full fledged solution, especially if there is no pressing need (see above). > Signed-off-by: John Watts <contact@jookia.org> > --- > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c > index a1ca3916f42bcc63b9ac7643e788d962ef360ca8..543311ffb1509face3fbfd069ded10933f254b9d 100644 > --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c > @@ -179,7 +179,7 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, > * At least on H6, some registers have some bits set by default > * which may cause issues. Clear them here. > */ > - writel(0, regs + TCON_TOP_PORT_SEL_REG); > + writel(0x20, regs + TCON_TOP_PORT_SEL_REG); Sorry, but that looks weird: First, please explain the 0x20. Is it bit 5? If yes, what does that bit mean? The commit message suggests you know that? And second: the comment above clearly states that those two writes just *clear* some registers, to have some sane base line. So please adjust this comment, and copy in some of the rationale from the commit message. Explaining things in the commit message is good (so thanks for that!), but having at least some terse technical explanations near the code, in a comment, is better. Cheers, Andre > writel(0, regs + TCON_TOP_GATE_SRC_REG); > > /* > > --- > base-commit: 98f7e32f20d28ec452afb208f9cffc08448a2652 > change-id: 20241108-tcon_fix-f0585ac9bae0 > > Best regards,
On Fri, Nov 08, 2024 at 11:53:57AM +0000, Andre Przywara wrote: > Hi John, Hi Andre! > Can you say *why* this patch is needed? Is there something broken that > needs fixing? Where does this show and why wasn't this a problem before? Oops, that's a good point. There is currently a bug where the LCD output will be tinted. I have full context here which I should have probably linked in the patch description: https://lore.kernel.org/linux-sunxi/Zn8GVkpwXwhaUFno@titan/T/#u > To be honest, given the isolation on this patch, I'd rather wait for this > full fledged solution, especially if there is no pressing need (see above). I'd be interested to hear if that's still the wanted solution given the link above. This currently blocks many people from having working LCD output. Doing it the proper way might be overkill for now unless someone deliberately tries to run two DEs to the same output. I haven't seen this use case. Allwinner kernel fork initially sets them up to values like these then makes sure both DEs can't be set to the same TCON. > > - writel(0, regs + TCON_TOP_PORT_SEL_REG); > > + writel(0x20, regs + TCON_TOP_PORT_SEL_REG); > > Sorry, but that looks weird: > First, please explain the 0x20. Is it bit 5? If yes, what does that bit > mean? The commit message suggests you know that? > > And second: the comment above clearly states that those two writes just > *clear* some registers, to have some sane base line. So please adjust this > comment, and copy in some of the rationale from the commit message. > Explaining things in the commit message is good (so thanks for that!), but > having at least some terse technical explanations near the code, in a > comment, is better. Bit 5 is value 3 of TCON_TOP_PORT_DE1_MSK. The R40 datasheet explains the values of both masks as follows: 00: TCON_LCD0 01: TCON_LCD1 10: TCON_TV0 11: TCON_TV1 So this sets DE1's input to DE0. > > Cheers, > Andre Thanks, John Watts
On 11/8/24 6:59 PM, John Watts wrote: > On Fri, Nov 08, 2024 at 11:53:57AM +0000, Andre Przywara wrote: >> Hi John, > > Hi Andre! > >> Can you say *why* this patch is needed? Is there something broken that >> needs fixing? Where does this show and why wasn't this a problem before? > > Oops, that's a good point. There is currently a bug where the LCD output will > be tinted. I have full context here which I should have probably linked in the > patch description: > > https://lore.kernel.org/linux-sunxi/Zn8GVkpwXwhaUFno@titan/T/#u > >> To be honest, given the isolation on this patch, I'd rather wait for this >> full fledged solution, especially if there is no pressing need (see above). > > I'd be interested to hear if that's still the wanted solution given the link > above. This currently blocks many people from having working LCD output. > > Doing it the proper way might be overkill for now unless someone deliberately > tries to run two DEs to the same output. I haven't seen this use case. > > Allwinner kernel fork initially sets them up to values like these then makes > sure both DEs can't be set to the same TCON. > >>> - writel(0, regs + TCON_TOP_PORT_SEL_REG); >>> + writel(0x20, regs + TCON_TOP_PORT_SEL_REG); >> >> Sorry, but that looks weird: >> First, please explain the 0x20. Is it bit 5? If yes, what does that bit >> mean? The commit message suggests you know that? >> >> And second: the comment above clearly states that those two writes just >> *clear* some registers, to have some sane base line. So please adjust this >> comment, and copy in some of the rationale from the commit message. >> Explaining things in the commit message is good (so thanks for that!), but >> having at least some terse technical explanations near the code, in a >> comment, is better. > > Bit 5 is value 3 of TCON_TOP_PORT_DE1_MSK. The R40 datasheet explains the > values of both masks as follows: > > 00: TCON_LCD0 > 01: TCON_LCD1 > 10: TCON_TV0 > 11: TCON_TV1 > > So this sets DE1's input to DE0. To add, 0x20 will be DE0 <--> LCD0 and DE1 <--> TV0. Below note (copied from R40) states the priority of the DE selection, which fails to work? Not sure, may be disabling CORE1_SCLK_GATE and CORE1_HCLK_GATE in de2-clk helps. With A133 following the same as T113 with single mixer without TV, still sets 0x20 in vendor kernel. copied from R40: Note: The priority of DE0 is higher than DE1. If TCON_LCD0 selects DE0 and DE1 as source at the same time, then DE0 will be used for the source of TCON_LCD0. Thanks, Parthiban > >> >> Cheers, >> Andre > > Thanks, > John Watts >
On Fri, Nov 08, 2024 at 07:36:16PM +0530, Parthiban wrote: > To add, 0x20 will be DE0 <--> LCD0 and DE1 <--> TV0. Below note (copied from > R40) states the priority of the DE selection, which fails to work? Not sure, > may be disabling CORE1_SCLK_GATE and CORE1_HCLK_GATE in de2-clk helps. > > With A133 following the same as T113 with single mixer without TV, still > sets 0x20 in vendor kernel. > > copied from R40: > Note: The priority of DE0 is higher than DE1. > If TCON_LCD0 selects DE0 and DE1 as source at the same time, then > DE0 will be used for the source of TCON_LCD0. Hi there, Yes that was a pretty bad typo, I meant to say DE1 to TV0 The prioritization seems broken in the T113 at least, it's racy from what I see in testing. I should note this in the patch too. I looked at the datasheets and kernel code briefly: I can't seem to figure out what SCLK/HCLK gating does and I don't think the kernel touches these registers which are gated by default. > Thanks, > Parthiban John Watts
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c index a1ca3916f42bcc63b9ac7643e788d962ef360ca8..543311ffb1509face3fbfd069ded10933f254b9d 100644 --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c @@ -179,7 +179,7 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, * At least on H6, some registers have some bits set by default * which may cause issues. Clear them here. */ - writel(0, regs + TCON_TOP_PORT_SEL_REG); + writel(0x20, regs + TCON_TOP_PORT_SEL_REG); writel(0, regs + TCON_TOP_GATE_SRC_REG); /*
On the D1 and T113 the TCON TOP cannot handle setting both DEs to a single output, even if the outputs are disabled. As a workaround assign DE1 to TVE0 by default. A full fix for this would include logic that makes sure both DEs never share the same output. Signed-off-by: John Watts <contact@jookia.org> --- drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- base-commit: 98f7e32f20d28ec452afb208f9cffc08448a2652 change-id: 20241108-tcon_fix-f0585ac9bae0 Best regards,