| Message ID | 20241113020233.3646527-1-ragavendra.bn@gmail.com (mailing list archive) |
|---|---|
| State | Rejected, archived |
| Headers | show |
| Series | clk:sophgo:clk-cv18xx-pll: fix unitialized u32 variable | expand |
Hi, Ragavendra, This patch should be dropped, right? I see a new patch https://lore.kernel.org/linux-clk/20241113184617.3745423-1-ragavendra.bn@gmail.com/ should have covered this. Suggest you reply this patch email and declare the dropping to avoid confusion. On 2024/11/13 10:02, Ragavendra wrote: > Initializing the val variable of type u32 as it was not initialized. > > Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") > Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com> > --- > drivers/clk/sophgo/clk-cv18xx-pll.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c > index 29e24098bf5f..04a0419cab4e 100644 > --- a/drivers/clk/sophgo/clk-cv18xx-pll.c > +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c > @@ -87,7 +87,7 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, > > static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) > { > - u32 val; > + u32 val = 0; > struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); > > return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
On Thu, Nov 14, 2024 at 07:36:21AM +0800, Chen Wang wrote: > Hi, Ragavendra, > > This patch should be dropped, right? I see a new patch https://lore.kernel.org/linux-clk/20241113184617.3745423-1-ragavendra.bn@gmail.com/ > should have covered this. > > Suggest you reply this patch email and declare the dropping to avoid > confusion. > > On 2024/11/13 10:02, Ragavendra wrote: > > Initializing the val variable of type u32 as it was not initialized. > > > > Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") > > Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com> > > --- > > drivers/clk/sophgo/clk-cv18xx-pll.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c > > index 29e24098bf5f..04a0419cab4e 100644 > > --- a/drivers/clk/sophgo/clk-cv18xx-pll.c > > +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c > > @@ -87,7 +87,7 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, > > static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) > > { > > - u32 val; > > + u32 val = 0; > > struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); > > return ipll_find_rate(pll->pll_limit, req->best_parent_rate, hi Chen, You are correct, please drop this patch email. -- Yours sincerely, Ragavendra N
diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c index 29e24098bf5f..04a0419cab4e 100644 --- a/drivers/clk/sophgo/clk-cv18xx-pll.c +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c @@ -87,7 +87,7 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit, static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - u32 val; + u32 val = 0; struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
Initializing the val variable of type u32 as it was not initialized. Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com> --- drivers/clk/sophgo/clk-cv18xx-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)