| Message ID | 20241114011310.3615-17-philmd@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | exec: Build up 'cputlb.h' and 'ram_addr.h' headers | expand |
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote: > Move CPU TLB related methods to "exec/cputlb.h". > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++ > include/exec/exec-all.h | 25 ------------------------- > target/i386/tcg/sysemu/excp_helper.c | 2 +- > target/microblaze/helper.c | 2 +- > 4 files changed, 30 insertions(+), 27 deletions(-) > > diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h > index f6205d5306..ae4798a017 100644 > --- a/include/exec/cputlb.h > +++ b/include/exec/cputlb.h > @@ -21,6 +21,8 @@ > #define CPUTLB_H > > #include "exec/cpu-common.h" > +#include "exec/hwaddr.h" > +#include "exec/memattrs.h" > #include "exec/vaddr.h" > > #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > @@ -80,4 +82,30 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); > void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, > CPUTLBEntryFull *full); > > +/** > + * tlb_set_page_with_attrs: > + * @cpu: CPU to add this TLB entry for > + * @addr: virtual address of page to add entry for > + * @paddr: physical address of the page > + * @attrs: memory transaction attributes > + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) > + * @mmu_idx: MMU index to insert TLB entry for > + * @size: size of the page in bytes > + * > + * Add an entry to this CPU's TLB (a mapping from virtual address > + * @addr to physical address @paddr) with the specified memory > + * transaction attributes. This is generally called by the target CPU > + * specific code after it has been called through the tlb_fill() > + * entry point and performed a successful page table walk to find > + * the physical address and attributes for the virtual address > + * which provoked the TLB miss. > + * > + * At most one entry for a given virtual address is permitted. Only a > + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only > + * used by tlb_flush_page. > + */ > +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, > + hwaddr paddr, MemTxAttrs attrs, > + int prot, int mmu_idx, vaddr size); > + > #endif > diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h > index 79649537b0..2b314d658b 100644 > --- a/include/exec/exec-all.h > +++ b/include/exec/exec-all.h > @@ -174,31 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, > uint16_t idxmap, > unsigned bits); > > -/** > - * tlb_set_page_with_attrs: > - * @cpu: CPU to add this TLB entry for > - * @addr: virtual address of page to add entry for > - * @paddr: physical address of the page > - * @attrs: memory transaction attributes > - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) > - * @mmu_idx: MMU index to insert TLB entry for > - * @size: size of the page in bytes > - * > - * Add an entry to this CPU's TLB (a mapping from virtual address > - * @addr to physical address @paddr) with the specified memory > - * transaction attributes. This is generally called by the target CPU > - * specific code after it has been called through the tlb_fill() > - * entry point and performed a successful page table walk to find > - * the physical address and attributes for the virtual address > - * which provoked the TLB miss. > - * > - * At most one entry for a given virtual address is permitted. Only a > - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only > - * used by tlb_flush_page. > - */ > -void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, > - hwaddr paddr, MemTxAttrs attrs, > - int prot, int mmu_idx, vaddr size); > /* tlb_set_page: > * > * This function is equivalent to calling tlb_set_page_with_attrs() > diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c > index da187c8792..cda0152b80 100644 > --- a/target/i386/tcg/sysemu/excp_helper.c > +++ b/target/i386/tcg/sysemu/excp_helper.c > @@ -20,7 +20,7 @@ > #include "qemu/osdep.h" > #include "cpu.h" > #include "exec/cpu_ldst.h" > -#include "exec/exec-all.h" > +#include "exec/cputlb.h" > #include "exec/page-protection.h" > #include "tcg/helper-tcg.h" > > diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c > index 5d3259ce31..27fc929bee 100644 > --- a/target/microblaze/helper.c > +++ b/target/microblaze/helper.c > @@ -20,7 +20,7 @@ > > #include "qemu/osdep.h" > #include "cpu.h" > -#include "exec/exec-all.h" > +#include "exec/cputlb.h" > #include "exec/page-protection.h" > #include "qemu/host-utils.h" > #include "exec/log.h" Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index f6205d5306..ae4798a017 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,8 @@ #define CPUTLB_H #include "exec/cpu-common.h" +#include "exec/hwaddr.h" +#include "exec/memattrs.h" #include "exec/vaddr.h" #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) @@ -80,4 +82,30 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full); +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @addr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @addr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 79649537b0..2b314d658b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -174,31 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @addr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @addr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index da187c8792..cda0152b80 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "tcg/helper-tcg.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..27fc929bee 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/host-utils.h" #include "exec/log.h"
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++ include/exec/exec-all.h | 25 ------------------------- target/i386/tcg/sysemu/excp_helper.c | 2 +- target/microblaze/helper.c | 2 +- 4 files changed, 30 insertions(+), 27 deletions(-)