diff mbox series

[v2,47/54] target/sh4: Convert to TCGCPUOps.tlb_fill_align

Message ID 20241114160131.48616-48-richard.henderson@linaro.org (mailing list archive)
State New
Headers show
Series accel/tcg: Convert victim tlb to IntervalTree | expand

Commit Message

Richard Henderson Nov. 14, 2024, 4:01 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sh4/cpu.h    |  8 +++++---
 target/sh4/cpu.c    |  2 +-
 target/sh4/helper.c | 24 +++++++++++++++++-------
 3 files changed, 23 insertions(+), 11 deletions(-)

Comments

Pierrick Bouvier Nov. 14, 2024, 6:54 p.m. UTC | #1 
On 11/14/24 08:01, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/sh4/cpu.h    |  8 +++++---
>   target/sh4/cpu.c    |  2 +-
>   target/sh4/helper.c | 24 +++++++++++++++++-------
>   3 files changed, 23 insertions(+), 11 deletions(-)
> 
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index d928bcf006..161efdefcf 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -22,6 +22,7 @@
>   
>   #include "cpu-qom.h"
>   #include "exec/cpu-defs.h"
> +#include "exec/memop.h"
>   #include "qemu/cpu-float.h"
>   
>   /* CPU Subtypes */
> @@ -251,9 +252,10 @@ void sh4_translate_init(void);
>   
>   #if !defined(CONFIG_USER_ONLY)
>   hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> -bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -                         MMUAccessType access_type, int mmu_idx,
> -                         bool probe, uintptr_t retaddr);
> +bool superh_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
> +                               vaddr addr, MMUAccessType access_type,
> +                               int mmu_idx, MemOp memop, int size,
> +                               bool probe, uintptr_t retaddr);
>   void superh_cpu_do_interrupt(CPUState *cpu);
>   bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
>   void cpu_sh4_invalidate_tlb(CPUSH4State *s);
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index 8f07261dcf..8ca8b90e3c 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -252,7 +252,7 @@ static const TCGCPUOps superh_tcg_ops = {
>       .restore_state_to_opc = superh_restore_state_to_opc,
>   
>   #ifndef CONFIG_USER_ONLY
> -    .tlb_fill = superh_cpu_tlb_fill,
> +    .tlb_fill_align = superh_cpu_tlb_fill_align,
>       .cpu_exec_interrupt = superh_cpu_exec_interrupt,
>       .cpu_exec_halt = superh_cpu_has_work,
>       .do_interrupt = superh_cpu_do_interrupt,
> diff --git a/target/sh4/helper.c b/target/sh4/helper.c
> index 9659c69550..543ac1b843 100644
> --- a/target/sh4/helper.c
> +++ b/target/sh4/helper.c
> @@ -792,22 +792,32 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>       return false;
>   }
>   
> -bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -                         MMUAccessType access_type, int mmu_idx,
> -                         bool probe, uintptr_t retaddr)
> +bool superh_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
> +                               vaddr address, MMUAccessType access_type,
> +                               int mmu_idx, MemOp memop, int size,
> +                               bool probe, uintptr_t retaddr)
>   {
>       CPUSH4State *env = cpu_env(cs);
>       int ret;
> -
>       target_ulong physical;
>       int prot;
>   
> +    if (address & ((1 << memop_alignment_bits(memop)) - 1)) {
> +        if (probe) {
> +            return false;
> +        }
> +        superh_cpu_do_unaligned_access(cs, address, access_type,
> +                                       mmu_idx, retaddr);
> +    }
> +
>       ret = get_physical_address(env, &physical, &prot, address, access_type);
>   
>       if (ret == MMU_OK) {
> -        address &= TARGET_PAGE_MASK;
> -        physical &= TARGET_PAGE_MASK;
> -        tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
> +        memset(out, 0, sizeof(*out));
> +        out->phys_addr = physical;
> +        out->prot = prot;
> +        out->lg_page_size = TARGET_PAGE_BITS;
> +        out->attrs = MEMTXATTRS_UNSPECIFIED;
>           return true;
>       }
>       if (probe) {

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index d928bcf006..161efdefcf 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -22,6 +22,7 @@ 
 
 #include "cpu-qom.h"
 #include "exec/cpu-defs.h"
+#include "exec/memop.h"
 #include "qemu/cpu-float.h"
 
 /* CPU Subtypes */
@@ -251,9 +252,10 @@  void sh4_translate_init(void);
 
 #if !defined(CONFIG_USER_ONLY)
 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                         MMUAccessType access_type, int mmu_idx,
-                         bool probe, uintptr_t retaddr);
+bool superh_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
+                               vaddr addr, MMUAccessType access_type,
+                               int mmu_idx, MemOp memop, int size,
+                               bool probe, uintptr_t retaddr);
 void superh_cpu_do_interrupt(CPUState *cpu);
 bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
 void cpu_sh4_invalidate_tlb(CPUSH4State *s);
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 8f07261dcf..8ca8b90e3c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -252,7 +252,7 @@  static const TCGCPUOps superh_tcg_ops = {
     .restore_state_to_opc = superh_restore_state_to_opc,
 
 #ifndef CONFIG_USER_ONLY
-    .tlb_fill = superh_cpu_tlb_fill,
+    .tlb_fill_align = superh_cpu_tlb_fill_align,
     .cpu_exec_interrupt = superh_cpu_exec_interrupt,
     .cpu_exec_halt = superh_cpu_has_work,
     .do_interrupt = superh_cpu_do_interrupt,
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 9659c69550..543ac1b843 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -792,22 +792,32 @@  bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     return false;
 }
 
-bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                         MMUAccessType access_type, int mmu_idx,
-                         bool probe, uintptr_t retaddr)
+bool superh_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out,
+                               vaddr address, MMUAccessType access_type,
+                               int mmu_idx, MemOp memop, int size,
+                               bool probe, uintptr_t retaddr)
 {
     CPUSH4State *env = cpu_env(cs);
     int ret;
-
     target_ulong physical;
     int prot;
 
+    if (address & ((1 << memop_alignment_bits(memop)) - 1)) {
+        if (probe) {
+            return false;
+        }
+        superh_cpu_do_unaligned_access(cs, address, access_type,
+                                       mmu_idx, retaddr);
+    }
+
     ret = get_physical_address(env, &physical, &prot, address, access_type);
 
     if (ret == MMU_OK) {
-        address &= TARGET_PAGE_MASK;
-        physical &= TARGET_PAGE_MASK;
-        tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
+        memset(out, 0, sizeof(*out));
+        out->phys_addr = physical;
+        out->prot = prot;
+        out->lg_page_size = TARGET_PAGE_BITS;
+        out->attrs = MEMTXATTRS_UNSPECIFIED;
         return true;
     }
     if (probe) {