| Message ID | 20241115-x1e80100-dp2-fix-v1-1-727b9fe6f390@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/dpu: fix x1e80100 intf_6 underrun/vsync interrupt | expand |
On Fri, Nov 15, 2024 at 01:55:13PM +0100, Stephan Gerhold wrote: > The IRQ indexes for the intf_6 underrun/vsync interrupts are swapped. > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16) is the actual underrun interrupt and > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17) is the vsync interrupt. > > This causes timeout errors when using the DP2 controller, e.g. > [dpu error]enc37 frame done timeout > *ERROR* irq timeout id=37, intf_mode=INTF_MODE_VIDEO intf=6 wb=-1, pp=2, intr=0 > *ERROR* wait disable failed: id:37 intf:6 ret:-110 > > Correct them to fix these errors and make DP2 work properly. > > Cc: stable@vger.kernel.org > Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support") > Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> This fixes the errors I was seeing with the third usb-c port on the x1e80100 CRD: Tested-by: Johan Hovold <johan+linaro@kernel.org> Johan
On Fri, Nov 15, 2024 at 01:55:13PM +0100, Stephan Gerhold wrote: > The IRQ indexes for the intf_6 underrun/vsync interrupts are swapped. > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16) is the actual underrun interrupt and > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17) is the vsync interrupt. > > This causes timeout errors when using the DP2 controller, e.g. > [dpu error]enc37 frame done timeout > *ERROR* irq timeout id=37, intf_mode=INTF_MODE_VIDEO intf=6 wb=-1, pp=2, intr=0 > *ERROR* wait disable failed: id:37 intf:6 ret:-110 > > Correct them to fix these errors and make DP2 work properly. > > Cc: stable@vger.kernel.org > Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support") > Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > This matches other DPU hardware, so Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index a3e60ac70689..d61895bb396f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -389,8 +389,8 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case = 24, - .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), - .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), }, { .name = "intf_7", .id = INTF_7, .base = 0x3b000, .len = 0x280,
The IRQ indexes for the intf_6 underrun/vsync interrupts are swapped. DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16) is the actual underrun interrupt and DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17) is the vsync interrupt. This causes timeout errors when using the DP2 controller, e.g. [dpu error]enc37 frame done timeout *ERROR* irq timeout id=37, intf_mode=INTF_MODE_VIDEO intf=6 wb=-1, pp=2, intr=0 *ERROR* wait disable failed: id:37 intf:6 ret:-110 Correct them to fix these errors and make DP2 work properly. Cc: stable@vger.kernel.org Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- base-commit: 744cf71b8bdfcdd77aaf58395e068b7457634b2c change-id: 20241115-x1e80100-dp2-fix-beb12c6dcac9 Best regards,