Message ID | 20241116154546.85761-1-hdegoede@redhat.com (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | [v2] platform/x86: p2sb: Cache correct PCI bar for P2SB on Gemini Lake | expand |
On Sat, 16 Nov 2024 16:45:46 +0100, Hans de Goede wrote: > Gemini Lake (Goldmont Plus) is an Apollo Lake (Goldmont) derived design and > as such has the P2SB at device.function 13.0, rather then at the default > 31.1, just like Apollo Lake. > > At a mapping to P2SB_DEVFN_GOLDMONT to p2sb_cpu_ids[] for Goldmont Plus, > so that the correct PCI bar gets cached. > > [...] Thank you for your contribution, it has been applied to my local review-ilpo branch. Note it will show up in the public platform-drivers-x86/review-ilpo branch only once I've pushed my local branch there, which might take a while. The list of commits applied: [1/1] platform/x86: p2sb: Cache correct PCI bar for P2SB on Gemini Lake commit: c6a2b4fcec5f2d80b0183fae1117f06127584c28 -- i.
diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c index 31f38309b389..d51eb0db0626 100644 --- a/drivers/platform/x86/p2sb.c +++ b/drivers/platform/x86/p2sb.c @@ -25,6 +25,7 @@ static const struct x86_cpu_id p2sb_cpu_ids[] = { X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, P2SB_DEVFN_GOLDMONT), {} };