diff mbox series

[net-next,2/2] net: axienet: Add support for AXI 2.5G MAC

Message ID 20241118081822.19383-3-suraj.gupta2@amd.com (mailing list archive)
State New
Delegated to: Netdev Maintainers
Headers show
Series Add support for AXI 2.5G ethernet | expand

Checks

Context Check Description
netdev/series_format success Posting correctly formatted
netdev/tree_selection success Clearly marked for net-next
netdev/ynl success Generated files up to date; no warnings/errors; no diff in generated;
netdev/fixes_present success Fixes tag not required for -next series
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 3 this patch: 3
netdev/build_tools success No tools touched, skip
netdev/cc_maintainers warning 1 maintainers not CCed: linux@armlinux.org.uk
netdev/build_clang success Errors and warnings before: 3 this patch: 3
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/deprecated_api success None detected
netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success No Fixes tag
netdev/build_allmodconfig_warn success Errors and warnings before: 6 this patch: 6
netdev/checkpatch warning WARNING: line length of 83 exceeds 80 columns WARNING: line length of 89 exceeds 80 columns WARNING: line length of 94 exceeds 80 columns
netdev/build_clang_rust success No Rust files in patch. Skipping build
netdev/kdoc success Errors and warnings before: 3 this patch: 3
netdev/source_inline success Was 0 now: 0
netdev/contest success net-next-2024-11-18--12-00 (tests: 789)

Commit Message

Suraj Gupta Nov. 18, 2024, 8:18 a.m. UTC 
Add AXI 2.5G MAC support, which is an incremental speed upgrade
of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
If max-speed property is missing, 1G is assumed to support backward
compatibility.

Co-developed-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
 drivers/net/ethernet/xilinx/xilinx_axienet.h  |  4 +++-
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 24 +++++++++++++++----
 2 files changed, 22 insertions(+), 6 deletions(-)

Comments

Radhey Shyam Pandey Nov. 18, 2024, 2:42 p.m. UTC | #1 
> -----Original Message-----
> From: Suraj Gupta <suraj.gupta2@amd.com>
> Sent: Monday, November 18, 2024 1:48 PM
> To: andrew+netdev@lunn.ch; davem@davemloft.net; edumazet@google.com;
> kuba@kernel.org; pabeni@redhat.com; Simek, Michal <michal.simek@amd.com>;
> sean.anderson@linux.dev; Pandey, Radhey Shyam
> <radhey.shyam.pandey@amd.com>; horms@kernel.org
> Cc: netdev@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; git (AMD-Xilinx) <git@amd.com>; Katakam, Harini
> <harini.katakam@amd.com>
> Subject: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC
> 
> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> If max-speed property is missing, 1G is assumed to support backward
> compatibility.
> 
> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!
> ---
>  drivers/net/ethernet/xilinx/xilinx_axienet.h  |  4 +++-
>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 24 +++++++++++++++----
>  2 files changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h
> b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> index d64b8abcf018..ebad1c147aa2 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> @@ -274,7 +274,7 @@
>  #define XAE_EMMC_RX16BIT	0x01000000 /* 16 bit Rx client enable */
>  #define XAE_EMMC_LINKSPD_10	0x00000000 /* Link Speed mask for 10 Mbit */
>  #define XAE_EMMC_LINKSPD_100	0x40000000 /* Link Speed mask for
> 100 Mbit */
> -#define XAE_EMMC_LINKSPD_1000	0x80000000 /* Link Speed mask for
> 1000 Mbit */
> +#define XAE_EMMC_LINKSPD_1000_2500	0x80000000 /* Link Speed
> mask for 1000 or 2500 Mbit */
> 
>  /* Bit masks for Axi Ethernet PHYC register */
>  #define XAE_PHYC_SGMIILINKSPEED_MASK	0xC0000000 /* SGMII link
> speed mask*/
> @@ -542,6 +542,7 @@ struct skbuf_dma_descriptor {
>   * @tx_ring_tail: TX skb ring buffer tail index.
>   * @rx_ring_head: RX skb ring buffer head index.
>   * @rx_ring_tail: RX skb ring buffer tail index.
> + * @max_speed: Maximum possible MAC speed.
>   */
>  struct axienet_local {
>  	struct net_device *ndev;
> @@ -620,6 +621,7 @@ struct axienet_local {
>  	int tx_ring_tail;
>  	int rx_ring_head;
>  	int rx_ring_tail;
> +	u32 max_speed;
>  };
> 
>  /**
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 273ec5f70005..52a3703bd604 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -2388,6 +2388,7 @@ static struct phylink_pcs *axienet_mac_select_pcs(struct
> phylink_config *config,
>  	struct axienet_local *lp = netdev_priv(ndev);
> 
>  	if (interface == PHY_INTERFACE_MODE_1000BASEX ||
> +	    interface == PHY_INTERFACE_MODE_2500BASEX ||
>  	    interface ==  PHY_INTERFACE_MODE_SGMII)
>  		return &lp->pcs;
> 
> @@ -2421,8 +2422,9 @@ static void axienet_mac_link_up(struct phylink_config
> *config,
>  	emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
> 
>  	switch (speed) {
> +	case SPEED_2500:
>  	case SPEED_1000:
> -		emmc_reg |= XAE_EMMC_LINKSPD_1000;
> +		emmc_reg |= XAE_EMMC_LINKSPD_1000_2500;
>  		break;
>  	case SPEED_100:
>  		emmc_reg |= XAE_EMMC_LINKSPD_100;
> @@ -2432,7 +2434,7 @@ static void axienet_mac_link_up(struct phylink_config
> *config,
>  		break;
>  	default:
>  		dev_err(&ndev->dev,
> -			"Speed other than 10, 100 or 1Gbps is not supported\n");
> +			"Speed other than 10, 100, 1Gbps or 2.5Gbps is not
> supported\n");
>  		break;
>  	}
> 
> @@ -2681,6 +2683,12 @@ static int axienet_probe(struct platform_device *pdev)
>  	lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node,
>  						   "xlnx,switch-x-sgmii");
> 
> +	ret = of_property_read_u32(pdev->dev.of_node, "max-speed", &lp-
> >max_speed);
> +	if (ret) {
> +		lp->max_speed = SPEED_1000;
> +		netdev_warn(ndev, "Please upgrade your device tree to use max-
> speed\n");
> +	}
> +
>  	/* Start with the proprietary, and broken phy_type */
>  	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
>  	if (!ret) {
> @@ -2854,7 +2862,8 @@ static int axienet_probe(struct platform_device *pdev)
>  			 "error registering MDIO bus: %d\n", ret);
> 
>  	if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||
> -	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
> +	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
> +	    lp->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
>  		np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0);
>  		if (!np) {
>  			/* Deprecated: Always use "pcs-handle" for pcs_phy.
> @@ -2882,8 +2891,13 @@ static int axienet_probe(struct platform_device *pdev)
> 
>  	lp->phylink_config.dev = &ndev->dev;
>  	lp->phylink_config.type = PHYLINK_NETDEV;
> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> MAC_ASYM_PAUSE |
> -		MAC_10FD | MAC_100FD | MAC_1000FD;
> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> MAC_ASYM_PAUSE;
> +
> +	/* Set MAC capabilities based on MAC type */
> +	if (lp->max_speed == SPEED_1000)
> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD |
> MAC_1000FD;
> +	else
> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
> 
>  	__set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces);
>  	if (lp->switch_x_sgmii) {
> --
> 2.25.1
Russell King (Oracle) Nov. 18, 2024, 3:56 p.m. UTC | #2 
On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> If max-speed property is missing, 1G is assumed to support backward
> compatibility.
> 
> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> ---

...

> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
> -		MAC_10FD | MAC_100FD | MAC_1000FD;
> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
> +
> +	/* Set MAC capabilities based on MAC type */
> +	if (lp->max_speed == SPEED_1000)
> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
> +	else
> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;

The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?

Normally, max speeds can be limited using phylink_limit_mac_speed()
which will clear any MAC capabilities for speeds faster than the
speed specified.
Sean Anderson Nov. 18, 2024, 4 p.m. UTC | #3 
On 11/18/24 10:56, Russell King (Oracle) wrote:
> On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
>> Add AXI 2.5G MAC support, which is an incremental speed upgrade
>> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
>> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
>> If max-speed property is missing, 1G is assumed to support backward
>> compatibility.
>> 
>> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
>> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
>> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
>> ---
> 
> ...
> 
>> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
>> -		MAC_10FD | MAC_100FD | MAC_1000FD;
>> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
>> +
>> +	/* Set MAC capabilities based on MAC type */
>> +	if (lp->max_speed == SPEED_1000)
>> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
>> +	else
>> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
> 
> The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?

It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
(2500Base-X). The MAC itself doesn't have this limitation AFAIK.

--Sean

> Normally, max speeds can be limited using phylink_limit_mac_speed()
> which will clear any MAC capabilities for speeds faster than the
> speed specified.
>
Russell King (Oracle) Nov. 18, 2024, 4:08 p.m. UTC | #4 
On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> On 11/18/24 10:56, Russell King (Oracle) wrote:
> > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> >> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> >> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
> >> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> >> If max-speed property is missing, 1G is assumed to support backward
> >> compatibility.
> >> 
> >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> >> ---
> > 
> > ...
> > 
> >> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
> >> -		MAC_10FD | MAC_100FD | MAC_1000FD;
> >> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
> >> +
> >> +	/* Set MAC capabilities based on MAC type */
> >> +	if (lp->max_speed == SPEED_1000)
> >> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
> >> +	else
> >> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
> > 
> > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> 
> It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> (2500Base-X). The MAC itself doesn't have this limitation AFAIK.

That means the patch is definitely wrong, and the proposed DT
change is also wrong.

If it's a limitation of the PCS, that limitation should be applied
via the PCS's .pcs_validate() method, not at the MAC level.
diff mbox series

Patch

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index d64b8abcf018..ebad1c147aa2 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -274,7 +274,7 @@ 
 #define XAE_EMMC_RX16BIT	0x01000000 /* 16 bit Rx client enable */
 #define XAE_EMMC_LINKSPD_10	0x00000000 /* Link Speed mask for 10 Mbit */
 #define XAE_EMMC_LINKSPD_100	0x40000000 /* Link Speed mask for 100 Mbit */
-#define XAE_EMMC_LINKSPD_1000	0x80000000 /* Link Speed mask for 1000 Mbit */
+#define XAE_EMMC_LINKSPD_1000_2500	0x80000000 /* Link Speed mask for 1000 or 2500 Mbit */
 
 /* Bit masks for Axi Ethernet PHYC register */
 #define XAE_PHYC_SGMIILINKSPEED_MASK	0xC0000000 /* SGMII link speed mask*/
@@ -542,6 +542,7 @@  struct skbuf_dma_descriptor {
  * @tx_ring_tail: TX skb ring buffer tail index.
  * @rx_ring_head: RX skb ring buffer head index.
  * @rx_ring_tail: RX skb ring buffer tail index.
+ * @max_speed: Maximum possible MAC speed.
  */
 struct axienet_local {
 	struct net_device *ndev;
@@ -620,6 +621,7 @@  struct axienet_local {
 	int tx_ring_tail;
 	int rx_ring_head;
 	int rx_ring_tail;
+	u32 max_speed;
 };
 
 /**
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 273ec5f70005..52a3703bd604 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2388,6 +2388,7 @@  static struct phylink_pcs *axienet_mac_select_pcs(struct phylink_config *config,
 	struct axienet_local *lp = netdev_priv(ndev);
 
 	if (interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX ||
 	    interface ==  PHY_INTERFACE_MODE_SGMII)
 		return &lp->pcs;
 
@@ -2421,8 +2422,9 @@  static void axienet_mac_link_up(struct phylink_config *config,
 	emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
 
 	switch (speed) {
+	case SPEED_2500:
 	case SPEED_1000:
-		emmc_reg |= XAE_EMMC_LINKSPD_1000;
+		emmc_reg |= XAE_EMMC_LINKSPD_1000_2500;
 		break;
 	case SPEED_100:
 		emmc_reg |= XAE_EMMC_LINKSPD_100;
@@ -2432,7 +2434,7 @@  static void axienet_mac_link_up(struct phylink_config *config,
 		break;
 	default:
 		dev_err(&ndev->dev,
-			"Speed other than 10, 100 or 1Gbps is not supported\n");
+			"Speed other than 10, 100, 1Gbps or 2.5Gbps is not supported\n");
 		break;
 	}
 
@@ -2681,6 +2683,12 @@  static int axienet_probe(struct platform_device *pdev)
 	lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node,
 						   "xlnx,switch-x-sgmii");
 
+	ret = of_property_read_u32(pdev->dev.of_node, "max-speed", &lp->max_speed);
+	if (ret) {
+		lp->max_speed = SPEED_1000;
+		netdev_warn(ndev, "Please upgrade your device tree to use max-speed\n");
+	}
+
 	/* Start with the proprietary, and broken phy_type */
 	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
 	if (!ret) {
@@ -2854,7 +2862,8 @@  static int axienet_probe(struct platform_device *pdev)
 			 "error registering MDIO bus: %d\n", ret);
 
 	if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||
-	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
+	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+	    lp->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
 		np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0);
 		if (!np) {
 			/* Deprecated: Always use "pcs-handle" for pcs_phy.
@@ -2882,8 +2891,13 @@  static int axienet_probe(struct platform_device *pdev)
 
 	lp->phylink_config.dev = &ndev->dev;
 	lp->phylink_config.type = PHYLINK_NETDEV;
-	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
-		MAC_10FD | MAC_100FD | MAC_1000FD;
+	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
+
+	/* Set MAC capabilities based on MAC type */
+	if (lp->max_speed == SPEED_1000)
+		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
+	else
+		lp->phylink_config.mac_capabilities |= MAC_2500FD;
 
 	__set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces);
 	if (lp->switch_x_sgmii) {