| Message ID | 20241118-dts_qcs615-v2-2-e62b924a3cbd@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Enable ethernet on qcs615 | expand |
On Mon, Nov 18, 2024 at 02:44:02PM +0800, Yijie Yang wrote: > Enable the ethernet node, add the phy node and pinctrl for ethernet. > > Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 106 +++++++++++++++++++++++++++++++ > 1 file changed, 106 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > index ee6cab3924a6d71f29934a8debba3a832882abdd..299be3aa17a0633d808f4b5d32aed946f07d5dfd 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts > +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > @@ -5,6 +5,7 @@ > /dts-v1/; > > #include <dt-bindings/regulator/qcom,rpmh-regulator.h> > +#include <dt-bindings/gpio/gpio.h> > #include "qcs615.dtsi" > / { > model = "Qualcomm Technologies, Inc. QCS615 Ride"; > @@ -196,6 +197,60 @@ vreg_l17a: ldo17 { > }; > }; > > +ðernet { > + status = "okay"; > + > + pinctrl-0 = <ðernet_defaults>; > + pinctrl-names = "default"; > + > + phy-handle = <&rgmii_phy>; > + phy-mode = "rgmii"; That is unusual. Does the board have extra long clock lines? > + max-speed = <1000>; Why do you have this property? It is normally used to slow the MAC down because of issues at higher speeds. Andrew
On 2024-11-19 09:27, Andrew Lunn wrote: > On Mon, Nov 18, 2024 at 02:44:02PM +0800, Yijie Yang wrote: >> Enable the ethernet node, add the phy node and pinctrl for ethernet. >> >> Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 106 +++++++++++++++++++++++++++++++ >> 1 file changed, 106 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >> index ee6cab3924a6d71f29934a8debba3a832882abdd..299be3aa17a0633d808f4b5d32aed946f07d5dfd 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >> @@ -5,6 +5,7 @@ >> /dts-v1/; >> >> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> >> +#include <dt-bindings/gpio/gpio.h> >> #include "qcs615.dtsi" >> / { >> model = "Qualcomm Technologies, Inc. QCS615 Ride"; >> @@ -196,6 +197,60 @@ vreg_l17a: ldo17 { >> }; >> }; >> >> +ðernet { >> + status = "okay"; >> + >> + pinctrl-0 = <ðernet_defaults>; >> + pinctrl-names = "default"; >> + >> + phy-handle = <&rgmii_phy>; >> + phy-mode = "rgmii"; > > That is unusual. Does the board have extra long clock lines? Do you mean to imply that using RGMII mode is unusual? While the EMAC controller supports various modes, due to hardware design limitations, only RGMII mode can be effectively implemented. > >> + max-speed = <1000>; > > Why do you have this property? It is normally used to slow the MAC > down because of issues at higher speeds. According to the databoot, the EMAC in RGMII mode can support speeds of up to 1Gbps. > > Andrew
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ee6cab3924a6d71f29934a8debba3a832882abdd..299be3aa17a0633d808f4b5d32aed946f07d5dfd 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -5,6 +5,7 @@ /dts-v1/; #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/gpio/gpio.h> #include "qcs615.dtsi" / { model = "Qualcomm Technologies, Inc. QCS615 Ride"; @@ -196,6 +197,60 @@ vreg_l17a: ldo17 { }; }; +ðernet { + status = "okay"; + + pinctrl-0 = <ðernet_defaults>; + pinctrl-names = "default"; + + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + max-speed = <1000>; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x7>; + + interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>; + device_type = "ethernet-phy"; + reset-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + }; +}; + &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, @@ -210,6 +265,57 @@ &rpmhcc { clocks = <&xo_board_clk>; }; +&tlmm { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { + pins = "gpio113"; + function = "rgmii"; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio114"; + function = "rgmii"; + bias-pull-up; + }; + + rgmii-rx-pins { + pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; + function = "rgmii"; + bias-disable; + drive-strength = <2>; + }; + + rgmii-tx-pins { + pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; + function = "rgmii"; + bias-pull-up; + drive-strength = <16>; + }; + + phy-intr-pins { + pins = "gpio121"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; + + pps-pins { + pins = "gpio91"; + function = "rgmii"; + bias-disable; + drive-strength = <8>; + }; + + phy-reset-pins { + pins = "gpio104"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + }; +}; + &uart0 { status = "okay"; };
Enable the ethernet node, add the phy node and pinctrl for ethernet. Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 106 +++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+)